Industry has made significant progress advancing EUVL technology the past several years leading to its full adoption for N7 node production. To extend EUVL technology well into 3nm node and beyond, a new high-NA EUV platform is needed. These new EUVL scanner platforms plan to use anamorphic optics with 0.55NA, which introduces several additional mask related imaging complications. Current scanners have light incidence of 6°, while the new 0.55NA systems will use < 6° incidence. At mask level, the combination of EUV light at oblique incidence, absorber thickness, and non-uniform mirror reflectance through incidence angle, creates mask-induced imaging aberrations, known as mask 3D effects (M3D). Additionally, these high NA systems will have non-telecentricity, which has shown to cause H-V bias due to shadowing, pattern shift through focus, and image contrast loss due to apodization by the reflective mask coatings. All these factors point to the need of thinner EUV mask absorber, which will dramatically reduce these effects. A possible mitigation for the M3D effects is to use mask absorber materials with high extinction coefficient κ and refractive coefficient n close to unity. Current EUV masks use Ta-based absorber on top of MoSi reflective multilayer. Multiple studies have shown that optical constants for the 60nm Ta-based absorber thickness at EUV wavelength do not provide optimal wafer imaging for high NA platforms. Alternative absorbers with higher absorptivity than Ta, such as Ni, Co among others have been proposed and, from simulation work, have shown improved high NA imaging at < 40nm thickness. The replacement of Ta-based absorber by new alternative material is an arduous task for the mask industry. The new absorber material must not only meet improved imaging criteria, but it must also meet required material properties which makes its compatibility with different aspects of mask blank and mask manufacturing process very critical.
In this work, we have embarked on alternative thin absorber material evaluation and characterization studies to find and assess viability of new absorber material, which best meets EUV mask fabrication requirements for impending N3 and below advanced semiconductor device nodes. While number of high-k materials were considered and evaluated, material selection narrowed our focus on one unique composite material, which met our critical requirements of low EUV reflectivity, fast etching rate and high cleaning durability. Material evaluation consisted of studying mask process modules from absorber etch, ebeam patterning capability, post-exposure processing and cleaning, defect Inspection, and finally EUV wafer printability. In these studies, we also evaluated this new material for critical mask patterning performance looking at key metrics such as resolution, CD linearity, proximity, control (targeting and uniformity), and LER/LWR. We also characterized pattern fidelity looking at complex mask designs for 5nm node and beyond using internally developed advanced mask characterization methodology emphasizing 2D pattern characterization including sidewall angle (SWA) assessment of patterned absorber.
Mask technology is key to enabling the progression of advanced IC technology nodes into the realm beyond 7nm node logic. In particular, extreme ultraviolet lithography (EUVL) relies heavily on the mask in order to achieve adequate process window (PW) and final yields. In the EUVL environment, mask process development and verification becomes increasingly more difficult and costly. The mask manufacture costs are driven by multiple factors including significantly more expensive mask blanks and increased ebeam write times. Wafer verification of mask process improvements is very difficult with the relatively low number of early adopters of EUVL and high cost associated with processing non-product wafers with that technology. It is therefore useful for mask manufacturers and wafer lithographers to collaborate to develop low cost mask process screening techniques as a precursor to committing valuable EUV exposure time for final verification. Previously, we demonstrated that by utilizing a toolkit of mask and wafer analytical techniques known as advanced mask characterization and optimization (AMCO) , we were able to predict wafer defectivity on 1D and 2D metal structures and optimize a mask process to enable 30nm pitch interconnect in a single exposure step using EUVL . In this study, we use similar methodology to develop a mask process for beyond 7nm node logic contact and via layers. These structures pose a different set of challenges than the metal layer. Contact hole area loss, corner rounding (CR), and mask process-induced x-y error on asymmetric holes must be optimized to deliver the required capability. Additionally, sub-resolution assist features (SRAFs) become relevant at this node. Resolving these on the mask is critical. Here, we describe the development of a mask process to overcome these challenges. We use advanced modeling techniques including AMCO to characterize the process improvements and predict wafer performance. Mask process improvements that are characterized include both physical mask process components as well as write data optimization techniques, i.e. mask process correction (MPC).
Extreme ultraviolet lithography (EUVL) is entering an industry production phase for 7nm logic and is under development for next node logic and memory applications. A key benefit of EUVL for logic interconnect lithography comes from the ability to pattern the metal layer at aggressive pitch using a single exposure. We report here a mask process compatible with a 30nm pitch patterning module for the demanding sub 7nm node, single expose interconnect application. We found a large increase in mask to wafer image transfer sensitivity during the 32nm to 30nm pitch shrink development that led to increases in stochastic and systematic wafer defect generation mechanisms. In this work, we describe our steps to characterize, model and improve the mask related factors that reduce this sensitivity as part of a successful 30nm pitch patterning module demonstration. High resolution wide area electron beam mask inspection alongside a suite of advanced mask characterization and optimization(AMCO)tools were key elements in understanding mask process gaps and improvement opportunities. Critical mask parameters optimized in closed loop with wafer response included two and three dimensional pattern fidelity, line roughness and spatial variability. Mask critical dimension targeting was found to be a critical factor for delivering the yielding 30nm pitch wafer process and this targeting was tuned dynamically through mask and wafer co-optimization. Finally, the role of wafer anchored process simulation proved an invaluable guide for linking various mask error source mechanisms to the wafer response.
As nodes progress into the 7nm and below regime, extreme ultraviolet lithography (EUVL) becomes critical for all industry
participants interested in remaining at the leading edge. One key cost driver for EUV in the supply chain is the reflective
EUV mask. As of today, the relatively few end users of EUV consist primarily of integrated device manufactures (IDMs)
and foundries that have internal (captive) mask manufacturing capability. At the same time, strong and early participation
in EUV by the merchant mask industry should bring value to these chip makers, aiding the wide-scale adoption of EUV
in the future. For this, merchants need access to high quality, representative test vehicles to develop and validate their
own processes. This business circumstance provides the motivation for merchants to form Joint Development Partnerships
(JDPs) with IDMs, foundries, Original Equipment Manufacturers (OEMs) and other members of the EUV supplier
ecosystem that leverage complementary strengths. In this paper, we will show how, through a collaborative supplier JDP
model between a merchant and OEM, a novel, test chip driven strategy is applied to guide and validate mask level process
development. We demonstrate how an EUV test vehicle (TV) is generated for mask process characterization in advance
of receiving chip maker-specific designs. We utilize the TV to carry out mask process “stress testing” to define process
boundary conditions which can be used to create Mask Rule Check (MRC) rules as well as serve as baseline conditions
for future process improvement. We utilize Advanced Mask Characterization (AMC) techniques to understand process
capability on designs of varying complexity that include EUV OPC models with and without sub-resolution assist features
(SRAFs). Through these collaborations, we demonstrate ways to develop EUV processes and reduce implementation risks
for eventual mass production. By reducing these risks, we hope to expand access to EUV mask capability for the broadest
community possible as the technology is implemented first within and then beyond the initial early adopters.
This paper provides experimental measurements of through-focus pattern shifts between contact holes in a dense array and a surrounding pattern of lines and spaces using the SHARP actinic microscope in Berkeley. Experimental values for pattern shift in EUV lithography due to 3D mask effects are extracted from SHARP microscope images and benchmarked with pattern shift values determined by rigorous simulations.
As optical lithography is extended into 10nm and below nodes, advanced designs are becoming a key challenge for mask manufacturers. Techniques including advanced Optical Proximity Correction (OPC) and Inverse Lithography Technology (ILT) result in structures that pose a range of issues across the mask manufacturing process. Among the new challenges are continued shrinking Sub-Resolution Assist Features (SRAFs), curvilinear SRAFs, and other complex mask geometries that are counter-intuitive relative to the desired wafer pattern. Considerable capability improvements over current mask making methods are necessary to meet the new requirements particularly regarding minimum feature resolution and pattern fidelity. Advanced processes using the IMS Multi-beam Mask Writer (MBMW) are feasible solutions to these coming challenges. In this paper, we study one such process, characterizing mask manufacturing capability of 10nm and below structures with particular focus on minimum resolution and pattern fidelity.
As optical lithography is extended into 10nm and below nodes, advanced designs are becoming a key challenge for mask
manufacturers. Techniques including advanced optical proximity correction (OPC) and Inverse Lithography
Technology (ILT) result in structures that pose a range of issues across the mask manufacturing process. Among the
new challenges are continued shrinking sub-resolution assist features (SRAFs), curvilinear SRAFs, and other complex
mask geometries that are counter-intuitive relative to the desired wafer pattern. Considerable capability improvements
over current mask making methods are necessary to meet the new requirements particularly regarding minimum feature
resolution and pattern fidelity. Advanced processes using the IMS Multi-beam Mask Writer (MBMW) are feasible
solutions to these coming challenges. In this paper, Part 2 of our study, we further characterize an MBMW process for
10nm and below logic node mask manufacturing including advanced pattern analysis and write time demonstration.
Photomasks to support 45nm node circuit development will be needed by mid year 2007 to meet the most aggressive device development programs. Volume manufacturing of 45nm technology photomask, however, would not occur until 2-3 years later. Either case would require an advanced photomask lithography capability that can meet the 45nm node specifications. From a mask maker's perspective, a lithography tool platform that is flexible, that supports high resolution and can be ramped for throughput would be the best solution. In an effort to understand if a potential tool platform(s) will exist, Photronics performed characterization and assessment studies of all commercial mask pattern generator platforms. All mask pattern generator tools, including both e-beam and laser platforms, were evaluated for performance against 45nm node target specifications as defined by the International Technology Roadmap for Semiconductors.
It has been demonstrated that the write time for 50keV E-beam masks is a function of layout complexity including figure count, vertex count and total line edge. This study is aimed to improve model fitting by utilizing all the variables generated from CATS. A better correlation of R2 = 0.99 was achieved by including quadratic and interaction terms. The vertex model was then applied to estimate write time of various nano-imprint templates. Accuracy of the vertex model is much better than the numbers generated from E-beam tool software. A 90nm test layout was treated with a mask optimization (MO) algorithm. A 26% write time reduction was observed through shot count reduction. The advanced features of the new generation E-beam writing tool combined with mask layout optimization, allows the same level of mask cost even though the capital cost of the new tool set increased 25%.
Long write times have been an industry wide concern regarding rising mask costs. The purpose of this study is to develop a simple model that can predict mask write time precisely, without an e-beam writer. With a good understanding of the trade-offs between design complexity and write time, mask makers can work with mask designers more closely to simplify design and minimize mask cost. This work compared several basic models including calculations based on write area with a fixed e-beam shot size, a software estimation with a pre-set exposure, and a mask stage settling time. Our proposed model uses a completely different approach to examine the correlation between layout complexity (vertices count, total line edge, figure, etc.) through a CATS layout segmentation and actual write time. It is found that write time is a strong function of layout figure, vertex count and total line edge. Errors between actual write time and estimated write time from the new model reduced from 7% on average on the current production software to 3%. Additionally, the new model can operate independent of the writer type and without fractured data being transferred onto a writer. Also provided are a few case studies to evaluate the interaction between write time and basic shape/OPC (optical proximity correction). Using a simple design shape and a better data snapping strategy can reduce write time up to 10 fold for applications in nano-imprint template manufacturing. Several strategies to reduce mask cost are proposed.
It is suggested that the high cost of mask sets for 90nm and below technologies may restrict the application of technologies to a handful of high volume chips. Most of the cost for mask production is a result of the increased time to write and inspect (including defect disposition) a mask due to the large files that are created prior to mask writing. Stringent mask specifications needed for low k factor imaging drive protracted and costly yield learning curves for a
mask maker. The cost of different steps in the flow from design tape-out to final wafer test are analyzed and it is shown that limiting the reticle field size on critical layers could reduce net costs. The net die cost is lower as long as the number of processed wafers stays below a cutoff number. Costs can be further decreased by reducing the overall "figure count" (and hence writing time) for an ASIC chip by restricting the amount of OPC done on critical layers.
Dark field (i.e. hole and trench layer) lithographic capability is lagging that of bright field. The most common dark field solution utilizes a biased-up, standard 6% attenuated phase shift mask (PSM) with an under-exposure technique to eliminate side lobes. However, this method produces large optical proximity effects and fails to address the huge mask error enhancement factor (MEEF) associated with dark field layers. It also neglects to provide a dark field lithographic solution beyond the 130nm technology node, which must serve two purposes: 1) to increase resolution without reducing depth of focus, and 2) to reduce the MEEF. Previous studies have shown that by increasing the background transmission in dark field applications, a corresponding decrease in the MEEF was observed. Nevertheless, this technique creates background leakage problems not easily solved without an effective opaqueing scheme. This paper will demonstrate the advantages of high transmission lithography with various approaches. By using chromeless dark field scattering bars around contacts for image contrast and chromeless diffraction gratings in the background, high transmission dark field lithography is made possible. This novel layout strategy combined with a new, very high transmission attenuating layer provides a dark field PSM solution that extends 248nm lithography capabilities beyond what was previously anticipated. It is also more manufacturing-friendly in the mask operation due to the absence of tri-tone array features.
With the inherent advantages of good Critical Dimension (CD) control and good pattern fidelity, dry etching of Chrome-on- Quartz (COG) binary masks is necessary for production of 0.18um or below technology generation masks. Chrome dry etching process, however, tends to produce more defects than the traditional wet etch processes. We have conducted in-process defect inspection studies, which have identified several defect sources and have proposed process controls that minimize the number and size of defects from the entire dry etch process. This paper discusses the design of a defect test vehicle and describes an approach and methodology of defect inspection as a means of understanding the creation mechanisms of process related defects. A Lasertec Corporation (i)-line inspection system is employed along with different microscopy and metrology tools to identify and characterize these defects that can be attributed to the various steps in this entire dry etch process. Our results demonstrate that this approach of in-process inspection is very effective at identifying defects and their sources as they become evident at different process steps.
Recent advances in pattern placement accuracy by photomask lithography tools are requiring much tighter repeatability specifications from the metrology equipment used in the characterization and monitoring process of these reticle writing systems. As pattern positioning accuracy specifications for the next generation tools (i.e., MEBES 4500 and ALTA 3000) dip below the 40 nanometer mark, the metrology tool must maintain a pattern placement measurement precision four times smaller than the writing tool, or less than 10 nanometers to satisfy current industry standards. The newest line width and coordinate registration metrology tool from Nikon, the Laser XY-5i, can measure photomasks and reticles with sub-10 nanometer precision. Recent acceptance test results as well as long term stability data (2-4 months) from a tool in a production environment prove the XY-5i worthy to characterize and monitor the newest mask and reticle lithography tools. A road map for future improvements and specification reduction will show the XY-5i capable of meeting the industry's metrology needs well into the 0.25 micron device generation and beyond.