The critical role of flare in extreme ultraviolet (EUV) lithography is well known. In this work, the implementation of a robust flare metrology is discussed, and the proposed approach is qualified both in terms of precision and accuracy. The flare measurements are compared to full-chip simulations using a simplified single fractal point-spread function (PSF), and the parameters of the analytical PSF are optimized by comparing the simulation output to the experimental results. After flare map calibration, the matching of simulation and experiment in the flare range from 4 to 12% is quite good, clearly indicating an offset of about 3%. The origin of this offset is attributed to the presence of DUV light. An experimental estimate of the DUV component is found in good agreement with the predicted value.
The 22nm node will be patterned with very challenging Resolution Enhancement Techniques (RETs) such
as double exposure or double patterning. Even with those extreme RETs, the k1 factor is expected to be
less than 0.3. There is some concern in the industry that traditional edge-based simulate-then-move Optical
Proximity Correction (OPC) may not be up to the challenges expected at the 22nm node. Previous work
presented the advantages of a so-called inverse OPC approach when coupled with extreme RETs or
illumination schemes. The smooth mask contours resulting from inverse corrections were shown not to be
limited by topological identity, feedback locality, or fragment conformity. In short, inverse OPC can
produce practically unconstrained and often non-intuitive mask shapes. The authors will expand this
comparison between traditional and inverse OPC to include likely 22nm RETs such as double dipole
lithography and double patterning, comparing dimensional control through process window for each OPC
method. The impact of mask simplification of the inverse OPC shapes into shapes which can be reliably
manufactured will also be explored.
Device extraction and the quality of device extraction is becoming of increasing concern for integrated
circuit design flow. As circuits become more complicated with concomitant reductions in geometry, the
design engineer faces the ever burgeoning demand of accurate device extraction. For technology nodes of
65nm and below approximation of extracting the device geometry drawn in the design layout
polygons might not be sufficient to describe the actual electrical behavior for these devices, therefore
contours from lithographic simulations need to be considered for more accurate results.
Process window variations have a considerable effect on the shape of the device wafer contour, having an
accurate method to extract device parameters from wafer contours would still need to know which
lithographic condition to simulate. Many questions can be raised here like: Are contours that represent the
best lithography conditions just enough? Is there a need to consider also process variations? How do we
include them in the extraction algorithm?
In this paper we first present the method of extracting the devices from layout coupled with lithographic simulations. Afterwards a complete flow for circuit time/power analysis using lithographic contours is described. Comparisons between timing results from the conventional LVS method and Litho aware method are done to show the importance of litho contours considerations.