Even small defects on the main patterns can create killer defects on the wafer, whereas the same defect on or near the decorative patterns may be completely benign to the wafer functionality. This ambiguity often causes operators and engineers to put a mask "on hold" to be analyzed by an AIMS™ tool which slows the manufacturing time and increases mask cost. In order to streamline the process, mask shops need a reliable way to quickly identify the wafer impact of defects during mask inspection review reducing the number of defects requiring AIMS™ analysis.
Source Mask Optimization (SMO) techniques are now common on sub 20nm node critical reticle patterns These techniques create complex reticle patterns which often makes it difficult for inspection tool operators to identify the desired wafer pattern from the surrounding nonprinting patterns in advanced masks such as SMO, Inverse Lithography Technology (ILT), Negative Tone Development (NTD).
In this study, we have tested a system that generates aerial simulation images directly from the inspection tool images. The resulting defect dispositions from a program defect test mask along with numerous production mask defects have been compared to the dispositions attained from AIMS™ analysis. The results of our comparisons are presented, as well as the impact to mask shop productivity.
The 1Xnm technology node lithography is using SMO-ILT, NTD or more complex pattern. Therefore in mask defect inspection, defect verification becomes more difficult because many nuisance defects are detected in aggressive mask feature. One key Technology of mask manufacture is defect verification to use aerial image simulator or other printability simulation. AIMS™ Technology is excellent correlation for the wafer and standards tool for defect verification however it is difficult for verification over hundred numbers or more.
We reported capability of defect verification based on lithography simulation with a SEM system that architecture and software is excellent correlation for simple line and space.
In this paper, we use a SEM system for the next generation combined with a lithography simulation tool for SMO-ILT, NTD and other complex pattern lithography. Furthermore we will use three dimension (3D) lithography simulation based on Multi Vision Metrology SEM system. Finally, we will confirm the performance of the 2D and 3D lithography simulation based on SEM system for a photomask verification.
In a Photomask manufacturing process, mask defect inspection is an increasingly important topic for 193nm optical lithography. Further extension of 193nm optical lithography to the next technology nodes, staying at a maximum numerical aperture (NA) of 1.35, pushes lithography to its utmost limits. This extension from technologies like ILT and SMO requires more complex mask patterns. In mask defect inspection, defect verification becomes more difficult because many nuisance defects are detected in aggressive mask features. One of the solutions is lithography simulation like AIMS. An issue with AIMS, however, is the low throughput of measurement, analysis etc.
Optical lithography stays at 193nm with a numerical aperture of 1.35 for several more years before moving to
EUV lithography. Utilization of 193nm lithography for 45nm and beyond forces the mask shop to produce
complex mask designs and tighter lithography specifications which in turn make process control more
important than ever. High yield with regards to chip production requires accurate process control.
Critical Dimension Uniformity (CDU) is one of the key parameters necessary to assure good performance and
reliable functionality of any integrated circuit. There are different contributors which impact the total wafer
CDU, mask CD uniformity, resist process, scanner and lens fingerprint, wafer topography, etc.
In this paper, the wafer level CD metrology tool WLCD of Carl Zeiss SMS is utilized for CDU measurements
in conjunction with the CDC tool from Carl Zeiss SMS which provides CD uniformity correction. The
WLCD measures CD based on proven aerial imaging technology. The CDC utilizes an ultrafast femto-second
laser to write intra-volume shading elements (Shade-In ElementsTM) inside the bulk material of the mask. By
adjusting the density of the shading elements, the light transmission through the mask is locally changed in a
manner that improves wafer CDU when the corrected mask is printed.
The objective of this study is to evaluate the usage of these two tools in a closed loop process to optimize
CDU of the mask before leaving the mask shop and to ensure improved intra-field CDU at wafer level.
Mainly we present the method of operation and results for logic pattering by using these two tools.
This paper tries to clarify the requirements for Source-Mask co-Optimization (SMO) type complex masks for low k1
technology nodes using a dedicated test mask. The current status of mask CD requirements and inspection capability for
Free Form (FF) SRAFs which give wider process window are discussed by comparing with Rectangular Shape (RS)
SRAFs. From CD deviation analysis with CD bias change at both main and SRAF patterns, the importance of CD
control at entire SRAF is emphasized although the partial lack of SRAF seems to give less impact on the main pattern
lithography performance. It is also suggested that SRAF printability of FF-SRAF needs to be carefully controlled with
mask bias error consideration. To identify the defects which give impact on litho performance, simulation-based defect
printability prediction (M-LMC) using inspection images is evaluated and found to be an important enabler for complex
mask inspection. The simulation-image based defect analysis helps to reduce the nuisance defects, and greatly saves
analysis time of measurement on Aerial Image Measurement System (AIMSTM). To introduce the complex free form
mask into production, mask-writing shot-count reduction is also evaluated. It is shown that fragmentation using Model-
Based (MB) Mask Data Preparation (MDP) effectively reduces the mask writing shot counts with using overlapping of
At 32nm node and beyond, a common approach in defect inspection (high resolution inspection mode) to
cope with aggressively OPCed mask patterns including SRAFs, is the utilization of small pixel size
inspection. In fact the sensitivity is increased by using smaller pixel size for the high resolution
inspection, but at the same time the throughput of the defect inspection tool falls.
In this paper, we propose that one of the solutions to improve inspection throughput is pixel migration.
KLA-Tencor's TeraScan XR improves SNR (Signal to Noise Ratio) for higher sensitivity as
comparison with TeraScanHR, so that pixel migration is possible. For tool performance confirmation,
TeraScanXR has improved in defect sensitivity and SRAF MRC (Mask Rule Check) limitation as
comparison with TeraScanHR. We confirmed that pixel migration is one of the solutions to control
inspection time growth of next generation mask. For printability simulation of pixel migration, we
confirmed the possibility of Brion's Mask-LMC (Mask-Lithography Manufacturability Check) defect
classification by lower SNR image. For experiment to achieve higher sensitivity, we confirmed defect
sensitivity improvement with experimental condition and considered the model to achieve higher sensitivity.
EUV mask pattern inspection was investigated using current DUV reticle inspection tool. Designed
defect pattern of 65nm node and 45nm node were prepared. We compared inspection sensitivity
between before buffer etch pattern and after buffer etch pattern, and between die to die mode and die to
database mode. Inspection sensitivity difference was not observed between before buffer etch pattern
and after buffer etch pattern. In addition to defect inspection, wafer print simulation of program defect
was investigated. Simulation results were compared to inspection result. We confirmed current DUV
reticle inspection tool has potential for EUV mask defect inspection.