Extreme ultraviolet lithography (EUVL) is getting closer to practical use for mass production every year. For applying EUV lithography to manufacturing, productivity improvement is a critical challenge. Throughput and yield are important factors for productivity. EUV source power is steadily advancing year by year, bringing improvements in throughput. Furthermore, yield improvement is necessary for productivity enhancement. In order to improve the yield in EUV lithography processing, further improvement of defectivity and critical dimension (CD) uniformity is required. One of the initial layers to be printed with EUV will be contact hole, therefore, we are concentrating on the productivity improvements of that layer.
In our report at SPIE 2017, defect reduction was achieved using the latest rinse technology in the development process and in-film defectivity was improved with material dispense optimization on a 24 nm contact hole (CH) pattern. On the basis of the knowledge acquired from the previous evaluation, improvements have been taken a step further in this next evaluation. As a result, 96% of residue defect reduction and 42% of in -film particle defect reduction has been achieved by further rinse optimization and improvement of dispense system.
For the other aspect of yield improvement, CD uniformity control is one of the crucial factors. CD variations are comprised of several components such as wafer to wafer CD uniformity, field to field CD uniformity. To achieve CD uniformity target for manufacturing, we have optimized developing process with the latest technology. Then, 15% of field to field CD uniformity improvement and significant improvement of wafer to wafer CD uniformity are achieved.
Extreme ultraviolet lithography (EUVL) technology is getting closer to high volume manufacturing phase every year. In order to enhance the yield in EUV lithography process, further improvement of defectivity is required at the moment. In this paper, optimized rinse and new dispense system (NDS) have been applied to a 24nm contact hole (CH) pattern in order to achieve defect reduction. As a result, the optimized rinse reduced approximately 70 % of residue defects. In addition, NDS for coating process exhibited 80 % defect reduction in particles in the coating films of material such as SOC, SOG, and resist.
To make sure a baseline process will be ready for the evaluation of the NXE:3300, imec evaluates promising new EUV resist materials with regards to imaging, process window and line width roughness (LWR) performance. From those screening evaluations, highest performing materials meeting dose sensitivity requirements are selected to be installed on the coat/develop track. This work details the process optimization results of the different selected resist platforms with regards to full wafer processing. Evaluations are executed on the ASML NXE:3100 equipped with a laser-assisted discharge produced plasma source from XTREME technologies, and interfaced to a TEL CLEAN TRACKTM LITHIUS ProTM -EUV.
Previously, fundamental evaluations of the Extreme Ultra Violet (EUV) lithography process have been conducted using
the CLEAN TRACK ACT™ 12 coater/developer with the ASML EUV Alpha Demo Tool (ADT) at imec. In that
work, we confirmed the basic process sensitivities for the critical dimension (CD) and defectivity with EUV resists.
Ultimate resolution improvements were examined with TBAH and FIRM™ Extreme. Moving forward with this work,
the latest inline cluster is evaluated using the ASML NXE:3100 pre-production EUV scanner and the CLEAN
TRACK™ LITHIUS Pro™ -EUV coater/developer. The imec standard EUV baseline process has been evaluated for
manufacturability of CD uniformity control based on half pitch (HP) 27nm and ultimate resolution studies focusing on
HP 22nm. With regards to the progress of the improvement for EUV processing, we confirmed the effectiveness of
several novel concepts: FIRM™ Extreme10 showed increase in ultimate resolution and improvement in line width
roughness (LWR) and process window; Tokyo Electron LTD. (TEL) smoothing process for roughness reduction showed
17% improvement for line and space (L/S) patterns; and finally the new dispense method reduced patterned wafer
defectivity by over 50%.
In order to further understand the processing sensitivities of the EUV resist process, TEL and imec have continued their
collaborative efforts. For this work, TEL has delivered and installed the state of the art, CLEAN TRACK™ LITHIUS
Pro™ -EUV coater/developer to the newly expanded imec 300mm cleanroom in Leuven, Belgium. The exposures
detailed in this investigation were performed off-line to the ASML EUV Alpha Demo Tool (ADT) as well as on the inline
ADT cluster with CLEAN TRACK™ ACT™ 12 coater/developer. As EUV feature sizes are reduced, is it apparent
that there is a need for more precise processing control, as can be demonstrated in the LITHIUS Pro™ -EUV. In
previous work from this collaboration1, initial investigations from the ACT™ 12 work showed reasonable results;
however, certainly hardware and processing improvements are necessary for manufacturing quality processing
performance. This work continues the investigation into CDU and defectivity performance, as well as improvements to
the process with novel techniques such as advanced defect reduction (ADR), pattern collapse mitigation with FIRM™Extreme and resolution improvement with tetrabutylammoniumhydroxide (TBAH).
In this work we present insights into RLS trade-offs by combining experimental data mining and resist modeling and
simulation techniques with a development rate monitor (DRM). A DRM provides experimentally-determined
dissolution characteristics for a given resist process and potentially can be used to produce a more accurate model
description of the process. This work presents experimentally-determined dissolution characteristics for ultra-thin
(50nm) EUV resist films as a function of material type and developer conditions and their impact to RLS trade-offs.
Resist models are created with DRM data for its dissolution characteristics and used in subsequent simulations to gain
fundamental understanding of EUV lithographic performance. In addition to typical lithographic quality metrics
(exposure latitude, DOF), the interaction of resist properties (ie, de-protection kinetics and dissolution) with processing
techniques are also discussed. Finally, a description of the RLS trade-off with respect to resist properties and process
conditions is discussed.
The goal of this work is to use a combination of experiment and calibrated resist models to understand the impact of photo-acid generator (PAG) and sensitizer loading on the performance of a polymer bound PAG resist based processes for extreme ultraviolet (EUV) lithography. This paper describes construction of a chemically amplified resist model across 248 nm, 193 nm, and EUV imaging wavelengths. Using resist absorbance input as obtained from experiment and modeling, only the acid formation kinetics are allowed to vary across imaging wavelengths. This constraining system affords very good fitting results, which provides high confidence that the extracted parameters from the model have actual physical significance. The quantum efficiency for acid formation in EUV is found to be ∼8× higher than at 248 or 193 nm, due to the excitation mechanism by secondary electrons. Most notably for the polymer bound PAG system under study the model provides an extremely low acid diffusion length (∼8 nm), suggesting an excellent inherent resolution for this material. Next, resist models are created for a series of sensitizer containing polymer bound PAG formulations, where the sensitizer loading is systematically varied. Compared to the reference polymer bound PAG resist without sensitizer the efficiency of acid formation is significantly increased, without a negative impact on either resolution or linewidth roughness. For these materials the quantum efficiency of acid formation in EUV is found to be ∼12× higher than at 248 nm. In these formulations the impact of sensitizer loading on the sizing dose is found to be rather moderate. This may suggest that even at the lowest sensitizer loading studied the energy of the secondary electrons is already efficiently transferred to the PAGs.
The reduction of line width roughness (LWR) is a critical issue in developing resist materials for EUV lithography and
LWR represents a trade-off between sensitivity and resolution. Additional post pattern processing is expected as an LWR
reduction technique without impact to resolution or sensitivity. This paper reports the LWR reducing effect of a post-development
resist-smoothing process. Approximately 20% improvement in LWR for ArF immersion exposed resist patterns was achieved for two types of resist and two illumination conditions. The LWR after BARC etching in which
resist-smoothing was applied was decreased relative to the case in which smoothing was not applied. Resist-smoothing
process also reduced LWR of an EUV exposure resist pattern by approximately 10%. These results confirm that resistsmoothing
process is robust for different resists and illumination conditions.
This paper describes construction of a chemically amplified resist model across 248nm, 193nm and EUV imaging
wavelengths. Using resist absorbance input as obtained from experiment and modeling, only the acid formation kinetics
are allowed to vary across imaging wavelengths. This very constraining system affords very good fitting results, which
provides high confidence that the extracted parameters from the model have actual physical significance. The quantum
efficiency for acid formation in EUV is found to be ~8X higher than at 248 or 193nm, due to the excitation mechanism
by secondary electrons. Most notably for the polymer bound PAG system under study the model provides an extremely
low acid diffusion length (~7nm), suggesting an excellent inherent resolution for this material.
Next, resist models are created for a series of sensitizer containing polymer bound PAG formulations, where the
sensitizer loading is systematically varied. Compared to the reference polymer bound PAG resist without sensitizer the
efficiency of acid formation is significantly increased, without a negative impact on either resolution or line width
roughness. For the materials the quantum efficiency of acid formation in EUV is found to be ~12X higher than at 248nm.
In these formulations the impact of sensitizer loading on the sizing dose is found to be rather moderate. This may suggest
that even at the lowest sensitizer loading studied the energy of the secondary electrons is already efficiently transferred to the PAGs.
As Extreme ultraviolet (EUV) lithography technology shows promising results below 40nm feature sizes, TOKYO
ELECTRON LTD.(TEL) is committed to understanding the fundamentals needed to improve our technology, thereby
enabling customers to meet roadmap expectations. TEL continues collaboration with imec for evaluation of
Coater/Developer processing sensitivities using the ASML Alpha Demo Tool for EUV exposures. The results from the
collaboration help develop the necessary hardware for EUV Coater/Developer processing. In previous work, processing
sensitivities of the resist materials were investigated to determine the impact on critical dimension (CD) uniformity and
defectivity. In this work, new promising resist materials have been studied and more information pertaining to EUV
exposures was obtained. Specifically, post exposure bake (PEB) impact to CD is studied in addition to dissolution
characteristics and resist material hydrophobicity. Additionally, initial results show the current status of CDU and
defectivity with the ADT/CLEAN TRACK ACTTM 12 lithocluster. Analysis of a five wafer batch of CDU wafers shows
within wafer and wafer to wafer contribution from track processing. A pareto of a patterned wafer defectivity test gives
initial insight into the process defects with the current processing conditions. From analysis of these data, it's shown that
while improvements in processing are certainly possible, the initial results indicate a manufacturable process for EUV.
Through collaborative efforts ASML and TEL are continuously improving the process performance for the
LITHIUS Pro -i/ TWINSCAN XT:1900Gi litho cluster. In previous work from this collaboration, TEL and ASML
have investigated the CDU and defectivity performance for the 45nm node with high through put processing.
CDU performance for both memory and logic illumination conditions were shown to be on target for ITRS roadmap
specifications. Additionally, it was shown that the current defect metrology is able to measure the required defect size
of 30nm with a 90% capture rate. For the target through put of 180wph, no added impact to defectivity was seen from
the multi-module processing on the LITHIUS Pro -i, using a topcoat resist process. For increased productivity, a new
bevel cut strategy was investigated and shown to have no adverse impact while increasing the usable wafer surface.
However, with the necessity of double patterning for at least the next technology node, more stringent requirements are
necessary to prevent, in the worst case, doubling of the critical dimension variation and defectivity.
In this work, improvements in process performance with regards to critical dimension uniformity and defectivity are
investigated to increase the customer's productivity and yield for whichever double patterning scheme is utilized.
Specifically, TEL has designed, evaluated and proven the capability of the latest technology hardware for post exposure
bake and defect reduction. For the new post exposure bake hardware, process capability data was collected for 40nm
CD targets. For defectivity reduction, a novel concept in rinse technology and processing was investigated on
hydrophobic non top coat resists processes. Additionally, improvements to reduce micro bridging were evaluated.
Finally bevel rinse hardware to prevent contamination of the immersion scanner was tested.
Immersion lithography has been developed for 45nm technology node generation during the last several years. Currently, IC manufacturers are moving to high volume production using immersion lithography. Due to the demand of IC manufactures, as the critical dimension (CD) target size is shrinking, there are more stringent requirements for CD
control.
Post Exposure Bake (PEB) process, which is the polymer de-protection process after exposure, is one of the important processes to control the CD in the 193nm immersion lithography cluster. Because of the importance of the PEB process for CD uniformity, accurate temperature control is a high priority. Tokyo Electron LTD (TEL) has been studying the temperature control of PEB plates. From our investigation, total thermal history during the PEB process is a key point for controlling intra wafer and inter wafer CD [1]. Further, production wafers are usually warped, which leads to a nonuniform thermal energy distribution during the PEB process. So, it is necessary to correct wafer warpage during the baking process in order to achieve accurate CD control on production wafers. TEL has developed a new PEB plate for 45nm technology node mass production, which is able to correct wafer warpage. The new PEB plate succeeded in
controlling the wafer temperature on production wafers using its warpage control function.
In this work, we evaluated CD process capability using the wafer warpage control PEB plate, which is mounted on a
CLEAN TRACKTM LITHIUS ProTM-i (TEL) linked with the latest immersion exposure tool. The evaluation was performed together with an IC manufacturer on their 45nm production substrates in order to determine the true performance in production.
193nm(ArF) photoresist used for 90nm to 65nm nodes has shown many significant characteristics. Especially, higher sensitivity to PEB (Post Exposure Bake) temperatures compared to 248nm(KrF) photoresist is critical in CD control. We classified CD budget of each process in coater/developer regarding 193nm photoresist to examine each factor’s influence. As a result, it’s found that PEB makes up about 70% of the track-related CD factors. This fact indicates the importance of PEB in 193nm process. We made improvements to inter and intra wafer for enhancing CD control in the 193nm process. Controlling chamber temperature in PEB process made 68.9% of improvement in CD variation of inter wafer. As for the intra wafer, the CD variation was improved 28.6% by modifying thermal history that has a great influence on PEB process. However, we assume that there are cases that don’t apply this budget since there are influences of the warped wafer and of flare in the exposure tool. In these cases, using a divided heater-type hotplate that we have been working on the development enables to make adjustment and results in 38.3% of improvement in intra wafer.
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