Overlap errors and sidel-lobe printing caused by the design rule reduction in the lithography using attenuated phase shift mask have become serious. Overlap errors and side-lobes can be simultaneously solved by the rule-based correction using scattering bars with the rules extracted from test patterns. Process parameters affecting the attPSM lithography simulation have been determined by the fitting method to the process data. Overlap errors have been solved applying the correction rules to the metal patterns overlapped with contact or via. Moreover, the optimal insertion rule of the scattering bars has made it possible to suppress the side-lobes and to enhance DOF at the same time. Compared to the existing Cr shield method, the proposed rule-based correction with scattering bars can reduce the process complexity and time for mask production.
A practical method to control the full chip level gate CD of a logic device with a 0.28 micrometer minimum design rule in DUV lithography is evaluated using an automatic optical proximity correction (OPC) software with empirical modeling. The CD variation on a chip results from the proximity and uniformity CD errors. The proximity error occupying more than 40% of total CD variation is caused by the pattern geometry, resist process, and mask CD error. In this paper, the OPC has been applied to line width narrowing and line-end shortening. The line-end shortening has been corrected by only the line- end extension instead of adding serifs which can be mistaken for defects during mask inspection. From this work, 43% reduction of the CD variation induced by proximity in the 3(sigma) standard deviation has been achieved at the 14 nm correction unit. Furthermore, the focus margin of 1.2 micrometer after OPC has been guaranteed. The results of line- end correction show that the line-end extension correction is sufficient to correct the overlap mismatching between the active and gate layers.
As the minimum feature size in VLSI circuits is reduced less than the wavelength of the exposure light, resolution enhancement technologies (RETs) have been developed. Optical proximity correction (OPC), which is one of RETs, can correct the difference in line width between isolate lines and lines in a dense array. Among the factors of CD variation (i.e., the optical proximity effect, numerical aperture, partial coherence, swing effect, and CD error on a mask), we have found that the optical proximity effect causes a severe isolate-dense bias larger than 35 nm. The optical proximity effect was corrected using an automatic tool based on an optical behavioral model. To determine the optimum threshold intensity, test patterns with the various threshold values were produced and measured using SEM. From this experiment, a proper threshold has been chosen and applied to a full chip pattern except the cell area in the gate layer of an SRAM device, which is optimized by photo engineer's experience. Furthermore, a model recipe correcting only the line width was set up to prevent the increase of the e-beam data size in two dimensional correction. Up to 40% reduction of CD variation can be expected, considering that more than 50% of gate layer patterns have the error distribution of -10 nm to 10 nm after OPC.
KEYWORDS: Photomasks, Manufacturing, Optical simulations, Monte Carlo methods, Scattering, Convolution, Lithography, 3D modeling, Electron beams, Scanning electron microscopy
A three-dimensional electron-beam lithography simulator version 2.0 has been newly enhanced for the multiple exposure of the Gaussian round beam. Development model parameters of the poly(butene-1-sulfone) positive electron beam resist in the spin-spray type are extracted through the experiment and simulation. With these parameters, electron beam simulation is applied to the submicron photomask manufacturing. The Gaussian round beam with the spot size and the address size of 0.1 micrometer is exposed with the dose of 2 (mu) C/cm2 at 10 keV on the 4000 angstrom resist/1000 angstrom chrome/glass substrate and the development time is 50 sec. With respect to the CD linearity of L/S, an isolated line and space pattern, the two-dimensional simulation results agree well to the measured data. The three dimensional simulation for a contact hole test pattern of gigabit DRAMs is demonstrated and compared with the SEM micrograph of the experimental profile. The results show that this simulation approach is highly practical to photomask manufacturing applications.
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