The mask CD mean-to-target (MTT) has been widely adopted as one of the key metrics for the mask quality control. As more aggressive optical proximity correction (OPC) is applied to push the resolution limit, traditional CDSEM measurement-based metrology is not sufficient to characterize mask CD MTT, especially for complicated 2D patterns. In this paper, we present the method of using SEM image contours for the characterization of mask CD MTT. The full flow includes contour extraction from mask SEM images, contour-to-contour alignment, contour averaging and edge placement error (EPE) measurement of mask image contour against the target. The OPC Verify engine is employed to give fast EPE check at closely packed sampling sites along the target. We apply this method to evaluate mask CD MTT for the hotspot patterns from two masks. The generated mask CD MTT distribution histograms and color maps demonstrate a good correlation with the wafer defect counts.
With continued innovation of semiconductor processes, overlay control has become the most critical and challenging part. Advanced technology nodes require even tighter lithography overlay control, and therefore, high-order process corrections for inter-field (HOPC) and for intra-field (iHOPC) are adopted as a common solution to meet on-product overlay (OPO) specifications. High order corrections often require more measurement shots and more targets in field, which makes optical overlay metrology on scribe line targets the workhorse of overlay control due to its high throughput and low cost-of-ownership. This leads to the additional challenge that the measurement location also affects the accuracy of generated overlay corrections. For example, it is well known that there may be a spatially dependent offset between overlay on targets and the device. This is commonly called a non-zero offset (NZO) [1], which is a comparison between device overlay measured with the CD SEM after etching (AEI) and optical overlay measured on targets after litho (ADI). In addition, the position of targets could impact the validity of corrections modeled using these targets. The targets could be unevenly distributed in field, some targets huddle at an area, while not a single target appears at others. Hence, this kind of target layout has risks generating problematic field corrections at areas without enough targets. In this paper, we propose a hybrid method utilizing CDSEM overlay to fill in the position where optical overlay targets are deficient. With iHOPC model terms generated by optical overlay targets only, CDSEM metrology results from real devices reveal significantly larger overlay in areas with no targets. By means of this method, the mis-correction at locations where optical overlay targets are deficient is significantly restored, and consequently the OPO mean+3sigma is suppressed to <4nm. Furthermore, an inline control solution is proposed and implemented with the latest generation 5D Analyzer.
As the IC manufacturing enter sub 20nm tech nodes, DFM become more and more important to make sure more stable yield and lower cost. However, by introducing newly designed hardware (1980i etc) process chemical (NTD) and Control Algorithm (Focus APC) into the mature tech nodes such as 14nm/12nm, more process window and less process variations are expected for latecomer wafer fabs (Tier-2/3 companies) who just started the competition with Tier-1 companies. With improved weapons, latecomer companies are able to review their DFM strategy one more time to see whether the benefit from hardware/process/control algorithm improvement can be shared with designers In this paper, we use OPC simulation tools from different EDA suppliers to see the feasibility of transferring the benefits of hardware/process/control algorithm improvement to more relaxed design limitation through source mask optimization (SMO): 1) Better hardware: scanner (better focus/exposure variation), CMP (intrafield topo), Mask CD variation (relaxed MEEF spec), etc.; 2) New process: from positive tone development to negative tone development; 3) Better control schemes: holistic focus feedback, feedback/forward overlay control, high order CD uniformity improvement; Simulations show all those gains in hardware and process can be transferred into more relaxed design such as sub design rule structure process window include forbidden pitches (1D) and smaller E2E gaps (2D weak points).
KEYWORDS: Transmission electron microscopy, Calibration, Semiconducting wafers, Electron microscopes, Fin field effect transistors, Image filtering, Scanning electron microscopy, Etching, Image quality, Integrated circuits, Deep ultraviolet, 193nm lithography, Electro optical systems calibration, Precision measurement, Accuracy assessment
In the 14nm FinFET(Fin-shaped Field-Effect Transistor) node, SADP(Self-Aligned Double Patterning) technology has been introduced to produce Fin because of the exposure limit of 193nm DUV immersion lithography. As is known to all, pitch walking issue appears when the technology comes to SADP, so how to accurately measure pitch walking is particularly important. In this paper, we use CD-SEM(Critical Dimension Scanning Electron Microscope) to measure the CD(Critical Dimension) of Fin pitch inline, and evaluate different parameter settings or machine type to improve the accuracy of the measurement results. For sub-nanometer accuracy of line width measurement, TEM(Transmission Electron Microscope) image is used to calibrate the line width measurements as a kind of reference metrology.
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