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This new integrated flow consists of applying ILT to the difficult core region and traditional rule-based assist features (RBAFs) with OPC to the peripheral region of a DRAM contact layer. Comparisons of wafer results between the ILT process and the non-ILT process showed the lithographic benefits of ILT and its ability to enable a robust single patterning process for this low-k1 device layer. Advanced modeling with a negative tone develop (NTD) process achieved the accuracy levels needed for ILT to control feature shapes through dose and focus. Details of these afore mentioned results will be described in the paper.
When setting up the rules for RBAF, not all patterns are considered. Thus, applying RBAF for contact layers may result in decreased process margin for certain patterns since the same rule is applied globally. MBAF, on the other hand, can maximize the process margin for various patterns as it generates AF (Assist Feature) to locations that maximize the margin for the patterns considered. However, MBAF method is very sensitive to even a slight change of a target, which influences the locations of the AF. This leads to generating different OPCed CD of the main features, even for those that should not be affected by the changed target. Once the OPCed CD is changed, it is impossible to obtain the same mask CD even when the mask is manufactured with the same method. If this case occurs during mass production, the entire layer needs to be confirmed after each revision which leads to unnecessary time loss.
In this paper, we suggest a new OPC method to prevent this issue. With this flow, OPCed shapes of unchanged patterns remain the same while only the changed targets are OPCed and replaced into the corresponding location, while the boundaries between those regions are corrected using a model based boundary healing. This method can reduce the overall OPCTAT as well as the time spent in verifying the entire layout after each revision. Details of these results will be described in this paper. After further studies, this flow can also be applied to ILT.
In this paper, we are going to certify that the overlay values extracted from optical measurement cannot represent the circuit level overlay values. We will also demonstrate the possibility to correct misregistration between two layers using the overlay data obtained from the DBM system.
In this paper, we have compared various mark designs with real cell in terms of aberration sensitivity under the specific illumination condition. The specific illumination model was used for aberration sensitivity simulation while varying mask tones and target designs. Then, diffraction based simulation was conducted to analyze the effect of aberration sensitivity on the actual overlay values. The simulation results were confirmed by comparing the OL results obtained by diffraction based metrology with the cell level OL values obtained using Critical Dimension Scanning Electron Microscope.
One of the technologies is NTD(Negative Tone Development) which uses inverse development compared to PTD(Positive Tone Development). The exposed area is eliminated by positive developer in PTD, whereas the exposed area is remained in NTD. It is well known that NTD has better characteristics compared to PTD in terms of DOF(Depth of Focus) margin, MEEF(Mask Error Enhancement Factor), and LER(Line End Roughness) for both small contact holes and isolated spaces [1]. Contact hole patterning is especially more difficult than space patterning because of the lower image contrast and smaller process window [2]. Thus, we have focused on the trend of both NTD and PTD contact hole patterns in various environments. We have analyzed optical performance of both NTD and PTD according to size and pitch by SMO(Source Mask Optimization) software. Moreover, the simulation result of NTD process was compared with the NTD wafer level performance and the process window variation of NTD was characterized through both results. This result will be a good guideline to avoid DoF loss when using NTD process for contact layers with various contact types.
In this paper, we studied the impact of different sources on various combinations of pattern sizes and pitches while estimating DOF trends aside from source and pattern types.
In this paper, we introduce a new HSF method that is able to make OPC TAT shorter than the common HSF method. The new HSF method consists of two concepts. The first one is that OPC target point is controlled to fix HSP. Here, the target point should be moved to optimum position at where the edge placement error (EPE) can be 0 at critical points. Many parameters such as a model accuracy or an OPC recipe become the cause of larger EPE. The second one includes controlling of model offset error through target point adjustment. Figure 1 shows the case EPE is not 0. It means that the simulation contour was not targeted well after OPC process. On the other hand, Figure 2 shows the target point is moved -2.5nm by using target point control function. As a result, simulation contour is matched to the original layout. This function can be powerfully adapted to OPC procedure of memory and logic devices.
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