The integrated circuit (IC) manufacturing factories have measured overlay with conventional "box-in-box" (BiB) or "frame-in-frame" (FiF) structures for many years. Since UMC played as a roll of world class IC foundry service provider, tighter and tighter alignment accuracy specs need to be achieved from generation to generation to meet any kind of customers' requirement, especially according to International Technology Roadmap for Semiconductors (ITRS) 2003 METROLOGY section1. The process noises resulting from dishing, overlay mark damaging by chemical mechanism polishing (CMP), and the variation of film thickness during deposition are factors which can be very problematic in mark alignment. For example, the conventional "box-in-box" overlay marks could be damaged easily by CMP, because the less local pattern density and wide feature width of the box induce either dishing or asymmetric damages for the measurement targets, which will make the overlay measurement varied and difficult. After Advanced Imaging Metrology (AIM) overlay targets was introduced by KLA-Tencor, studies in the past shown AIM was more robust in overlay metrology than conventional FiF or BiB targets. In this study, the applications of AIM overlay marks under different process conditions will be discussed and compared with the conventional overlay targets. To evaluate the overlay mark performance against process variation on 65nm technology node in 300-mm wafer, three critical layers were chosen in this study. These three layers were Poly, Contact, and Cu-Metal. The overlay targets used for performance comparison were BiB and Non-Segmented AIM (NS AIM) marks. We compared the overlay mark performance on two main areas. The first one was total measurement uncertainty (TMU)3 related items that include Tool Induced Shift (TIS) variability, precision, and matching. The other area is the target robustness against process variations.
Based on the present study AIM mark demonstrated an equal or better performance in the TMU related items under our process conditions. However, when non-optimized tungsten CMP was introduced in the tungsten contact process, due to the dense grating line structure design, we found that AIM mark was much more robust than BiB overlay target.
Planarization of gap-filling materials for low-k dual damascene processes is getting more and more important due to the photoresist process window shrinking as the pitch and critical dimensions shrink. Defects, especially pattern collapses, will become a serious problem if there is no global planarization for low-k dual damascene processes. IC manufacturers and materials vendors have proposed several ways to improve the global planarization of gap filling, such as using materials with different viscosities, fine tuning gap-filling material coating recipes, and even using optical or chemical treatments to obtain global planarization. The effect of the different conformalities of the first and second coating materials on coating performance will be discussed.
As 6% attenuated phase shift masks (PSM) become commonly used in ArF advanced lithography for the 90nm Technology and mass production to print lines/ spaces as well as contacts, the specification and control of the phase angle and the width of the distribution of phase angles becomes critical to maintain the quality of the lithography process. The influence of the mean phase angle and the width of the distribution of phase angles on the best focus, the through pitch behavior and uniformity of the critical dimension (CD uniformity) has been studied experimentally using a 6% attenuated PSM whose phase angle has been affected by several reticle cleans. The results are consistent with aerial image simulations. Independent specifications for the mean phase angle and the width of the distribution of phase angles have been derived and could be applied for the production of masks in the future.
Due to the existing problems and delay of 157nm lithography tool, extension of the ArF (193nm) lithography process with resolution enhancement techniques (RET) should be considered for the 65nm generation lithography and beyond. The mature double-exposure lithography process based on dark-field alternating phase-shift mask (PSM) is one of the promising RET candidates, which is proven to be one of the production-ready strong phase-shifting techniques for current and future IC generations. In this paper, poly gate patterning with the minimum pitch of 160nm has been demonstrated with high numeric aperture (NA) and small partial coherence of ArF lithography along with a dark-field alternating PSM. For poly gate patterning of 65nm generation, optimum illumination settings are found for minimum pitch of 160nm. Through-pitch common process windows for gates with 65nm after-development-inspection (ADI) critical dimension (CD) at minimum pitch of 160nm can be reached larger than 0.30um depth of focus (DOF), which can be used for 65nm node production. Through-pitch proximity can be compensated by optical proximity correction (OPC). Line edge roughness (LER) can be improved a little by this dark-field alternating PSM technique. LER is found of strong aerial image contrast dependency. Shifter width is also chosen as optimum value to obtain the largest process windows and minimize the phase conflicts. 193nm Hi-NA or liquid immersion lithography is suggested to push the alternating PSM resolution limitation.
Two fundamentally different approaches for chemical ArF resist shrinkage are evaluated and integrated into process flows for 90 nm technology node. The chemical shrink and the corresponding gain in process window is studied in detail for different resist types with respect to CD uniformity through pitch, linearity and resist profiles. For both, SAFIER and RELACS material, the sensitivity of the shrink process with respect to the baking temperature is characterized by a temperature matrix to check process stability, and optimized conditions are found offering an acceptable amount of
shrinkage at contact and trench levels. For the SAFIER material, thermal flow contributes to the chemical shrink which is a function of the photoresist chemistry and its hydrodynamic properties depending on the resists’ glass transition temperature (Tg) and the baking temperature: at baking temperatures close to Tg, a proximity and pattern dependent shrink is observed. For a given resist, line-space patterns and contact holes shrink differently, and their resist profiles are affected significantly. Additionally, the chemical shrinkage depends on the size of contact holes and resist profile prior to the application of the SAFIER process. At baking temperatures below Tg some resists exhibit no shrink at all. The
RELACS technique offers a constant shrink for contacts at various pitches and sizes. This shrink can be moderately adjusted and controlled by varying the mixing bake temperature which is generally and preferably below the glass transistion temperature of the resist, therefore no resist profile degradation is observed. A manufacturable process with a shrink of 20nm using RELACS at the contact layer is demonstrated. Utilizing an increased reticle bias in combination
with an increased CD target prior to the chemical shrink, the common lithography process window at contact layer was increased by 0.15um. The results also indicate a possibility for an extension of the shrink to greater than 50nm for more advanced processes.
Each new technology node tests the limits of optical lithography. As exposure wavelength is reduced, new imaging techniques are needed to maximize resolution capabilities. The phase shift mask (PSM) is one such technique that is utilized to push the limits of optical lithography. Altering the optical phase of the light that transmits through a photo mask can increase the resolution of a lithographic image significantly. There are several types of phase shift mask and each has a general charateristic in which some transparent area of the mask are given 180° shift in optical phase relative to other nearby transparent areas. The interaction of the aerial images between two features with a relative phase difference of 180° create interference regions that can be used to printed images much closer together and with an increased depth of focus than that of a standard chrome-on-glass mask. An AAPSM is fabricated using a subtractive process in which the quartz substrate is etched to a given depth to produce the desired phase shift. However, intensity imbalances between the etched and non-etched regions due to sidewall scattering can cause resolution, phase and placement errors on the wafer. One method to balance the transmission is 40 nm undercut with 16 nm shifter width bias. Based on our previous study, 40 nm undercut with 16 nm shifter width bias showed an improved balance of intensities between the etched and non-etched regions. The object of this experiment is to implement the AAPSM with 40 nm undercut and 16 nm shifter width bias in SRAM product and the exposure wavelength is 193 nm. The main purpose is to proof the technology of AAPSM with 40 nm undercut and 16 nm shifter width bias in real product. Also verifying all issue of AAPSM in production. In this study, the image imbalance has been corrected via 40 nm undercut and 16 nm shifter width bias, and the DOF of AAPSM for wafer print performance is larger than binary mask. The DOF of AAPSM is about 0.5 μm and the conventional binary mask is 0.3μm.
In our previously published work, we investigated alternating-aperture PSM image intensity imbalance as function of various mask and optical parameters using rigorous electro-magnetic field (EMF) simulations. Results suggested that the imbalance could be effectively compensated through application of an optimized combination of undercut and a constant phase-shifter bias. In the effort of development and implementation of a production-ready image imbalance correction methodology, it is important to validate the accuracy of simulation-based predictions through correlation of results to experimental data. For this purpose, a test reticle containing various mask parameters as variables was designed and manufactured. The experimental data was obtained from SEM measurements of the exposed wafers, and results were compared to rigorous EMF simulation data. Based on results obtained, we propose and validate an image imbalance correction methodology to be implemented within the framework of the PSM - OPC manufacturing flow.
A multiple exposure with matching illumination settings has been applied to the advanced photo process. We combine some special illumination settings which are good for each specific duty ratio and produce a good through-pitch performance. For example, we can combine OAI for dense and conventional with low sigma for Iso to optimize through pitch performance. With this method we can fine tune all illumination parameters, including NA, sigma, exposure dose, focus and pupil type. For sub-wavelength photolithography, the proximity effect of single illumination setting causes limited DOF through pitch so a compromise between isolated and dense pattern performance must be taken. Traditional exposure method using a single illumination setting can not fulfill the optimal illumination setting for patterns at all pitches. With this invention using multi-illumination settings, we can combine multiple exposures with the advantage of different illumination settings to perform better process capability include DOF and proximity through all pitches. Experimental data shows that the single exposure DOF of isolated hole and dense hole are below 0.2um but DOF can be enlarged to 0.4um by multiple exposure. And we get smaller proximity effect at the same time.
A novel multiple resist patterning stacks (MURPAS) method has been applied on the copper, low-k dual damascene interconnection. Trench resist structures are directly patterned on the top of via resist layer without the resist interface intermixing using a cross-linked, high thermal resistance, negative-tone resist a the bottom via layer. A single etch step can transfer these integrated patterns into low-k substrate with a simplified resist stripping process and reduced risk of resist contamination to the low-k substrate. The gap-filling procedure for the positive-tone trench resist process, to avoid the via resist residue and the topography issue on the high aspect ratio via etched substrate, can be eliminated as the negative-tone trench resist in the via is not cross-linked and easy to be resolved. The interfield trench CD and trench profile uniformity can be consistently controlled since there is less process variation for the trench patterning. Overall, this integrated process requires a thinner resist thickness for the dual damascene pattern etch with an enlarged lithography process window for the resolution limit, mask error enhance factor, DOF, and line edge roughness for both via and trench lithography. Applications of MURPAS methods on double-exposure resolution enhanced technology (RET) such as the rectangular cell array and the aggressive assistant features for trench and hole patterns are also be studied.