Introduction and problem statement
Given that EUV lithography allows printing smaller Critical Dimension (CD) features, it can result in non-normal distributed CD populations on ADI wafers [Civay SPIE AL 2014], leading to errors in predicted failure rates [Bristol SPIE AL 2017]. As a result, there is a need to quantify the actual behavior of the CD population extremes by means of massive metrology [Dillen EUVL 2018]. Not only allows this to study the CD distribution, we can in parallel also evaluate pattern quality and the failure mechanisms leading to defects. This massive metrology method provides an accurate failure rate based on CD, and enables new possibilities to define a failure rate based on different metrics in a single measurement.
We analyze the CD uniformity of pillars in polar coordinates using a global waveform based thresholding strategy. In conjunction with this CD information, we also evaluated the print quality of each individual measured feature.
Fig 1. In line detected anomalies and failure definitions
As we gather this information during the measurement of CD, we can limit the additional measurement overhead to neglectable levels.
Application and outlook
We will show how we can leverage this to determine a defect based process window and relations of failure mechanisms through process conditions (see figure 2). When we take failures in a CH dataset into account, we illustrate the effect on the shape of a large dataset distribution in figure 3.
Fig 2. Defect identification for a through exposure dose experiment of pillars. For each condition >13k pillars where measured. The plot clearly shows an asymmetric behavior due to different failure mechanisms at low and high energy. The 2 vertical lines at relative energies 0.93 and 1.05 times nominal indicate the low defect process window.
Fig 3. A distribution of measured regular grid dense CH. The red line is the unfiltered CD data, the blue line is the shape of the distribution after filtering individual CH measurements that have a much lower contrast than expected.
We evaluate through simulations and experimental data the impact of process non-idealities with a particular attention to mask CD uniformity for 44 nm pitch DRAM contact hole array. Several millions of contact holes are simulated with PROLITH after full-physical stochastic process calibration. Process Windows, LCDU and failure rates are compared at nominal conditions, assuming no variation in process parameters vs. the stochastic process variation obtained by inclusion of perturbations of process parameters. The simulations are repeated including Gaussian distributed mask CD variations. Skewness, kurtosis, and failure rates are calculated..
Illumination source optimization is a very fundamental task in wafer lithography. By optimizing the incidence angles at the reticle, the combined diffraction behavior of mask and projection optics can be modified. One of the most critical parameter to control in EUV lithography is contrast at best and through focus as this drives the stochastic effects. In this work, we will look at the illumination source optimization for staggered CH and pillars for DRAM applications driven by fundamental considerations at diffraction level.
As we presented in the last conference, it is much difficult to get down the k1 limit of EUV lithography compared to that of optical lithography especially recent immersion lithography. Even though current 0.33NA NXE3300 tool has enhanced aberration characteristics and variable illumination mode than its predecessor, ADT and NXE3100, still there are limitations related with resolution capability of EUV lithography. First of all, photon shot noise and immature resist performances play an important role in patterning of very fine patterns. As already known, low sensitivity resists have been widely used to reduce shot noise. However, when considering productivity in EUV lithography, high sensitivity resists are inevitable, so it is necessary to increase image contrast by reducing scanner blur like aberration, M3D, stray light et al. We have investigated the impact of aberration and limitation in illumination pupil fill ratio in EUV. In particular, the aberration sensitivity is different by the illumination conditions, this was intensified when using the particular pupil. Because the lens calibration is conducted with standard illumination condition in NXE3300, it is necessary to consider different aberration sensitivity in accordance with pattern and used pupil condition in EUV lithography. To ensure the process margin of tech node close to limit, a flexpupil with low pupil fill ratio (PFR) than 0.2 were required. Hence in order to avoid through-put loss at this condition, the new concept of the illuminator design is required without light loss. Contamination of collector mirror can affect the patterning also. We will also report about the patterning effect of pupil deformation by degraded collector in low PFR condition.
EUV lithography (EUVL) is the most promising technology to extend the resolution limit, and is expected to be used if the enough source power is delivered and mask defect mitigation method is developed. However, even in that case, the number of EUV steps will be restricted by its high cost, and ArF immersion will still take a major role in the chip manufacturing. Therefore, it is important to check and improve the mix-match overlay (MMO) between EUV and ArF immersion steps. In this paper, we evaluate EUV MMO with ArF immersion system by comparing with dedicated chuck overlay (DCO). The major contributors on MMO are random and field component from overlay analysis. MMO is expected to be below 3nm by applying 18para CPETM(correction per exposure) and RegCTM(Registraion error correction). We consider High oder CPETM need to be developed for further improvement.
In preparation for EUV lithography (EUVL) in high volume manufacturing, a preproduction ASML NXE:3100 step-and- scan system was used to assess overlay performance under mix-and-match between EUV and ArF lithography, which will be critical for the successful insertion of EUV lithography into high volume 1x node production. Overlay sources of variation associated with EUV were investigated, including mask pattern-placement error (PPE), scan direction, and processing order. Furthermore, this study also looks into overlay control strategy development specifically for EUV/ArF mix-and-match lithography. Systematic and random overlay components will be discussed, as well as possible overlay modeling and control options.
ASML NXE3100 has been introduced for EUV Pre-Production, and ASML NXE3300 for High Volume Manufacturing will be installed from this year. EUV mask defect control is the one of the concerns for introducing EUVL to device manufacturing, for current EUV mask defect level is too high to accept for device volume production. EUV mask defects
come from mask blank, mask process and mask handling. To have reduced mask defect level, quality control of blank
mask, optimization of EUV mask process and improvement of EUV mask handling need to be ready. In this paper, we analyze printed defects exposed from EUV full field mask at NXE3100. For this analysis we trace mask defects from mask to wafer printing. From this we will show current EUV mask’s defect type and numbers. Acceptable defect type, size and numbers for device manufacturing with EUVL will be shown. Through investigating printing result of natural ML defects, realistic level of natural ML defects will be shown.