Continuous scaling of CMOS process technology to 7nm (and below) has introduced new constraints and challenges in determining Design-for-Yield (DFY) solutions. In this work, traditional solutions such as improvements in redundancy and in compensating target designs for low process window margins are extended to meet the additional constraints of complex 7nm design rules. Experiments conducted on 7nm industrial designs demonstrate that the proposed solution achieves 9.1%-41% redundant-via-rate improvements while ensuring all 7nm design rule constraints are met.
As patterning for advanced processes becomes more challenging, designs must become more process-aware. The
conventional approach of running lithography simulation on designs to detect process hotspots is prohibitive in terms of
runtime for designers, and also requires the release of highly confidential process information. Therefore, a more
practical approach is required to make the In-Design process-aware methodology more affordable in terms of
maintenance, confidentiality, and runtime. In this study, a pattern-based approach is chosen for Process Hotspot Repair
(PHR) because it accurately captures the manufacturability challenges without releasing sensitive process information.
Moreover, the pattern-based approach is fast and well integrated in the design flow. Further, this type of approach is very
easy to maintain and extend. Once a new process weak pattern has been discovered (caused by Chemical Mechanical
Polishing (CMP), etch, lithography, and other process steps), the pattern library can be quickly and easily updated and
released to check and fix subsequent designs.
This paper presents the pattern matching flow and discusses its advantages. It explains how a pattern library is created
from the process weak patterns found on silicon wafers. The paper also discusses the PHR flow that fixes process
hotspots in a design, specifically through the use of pattern matching and routing repair.