Process and reliability risks have become critically important during mass production at advanced technology nodes even with Extreme Ultraviolet Lithography (EUV) illumination. In this work, we propose a design-for-manufacturability solution using a set of new rules to detect high risk design layout patterns. The proposed methods improve design margins while avoiding area overhead and complex design restrictions. In addition, the proposed method introduces an in-design pattern replacement with automatically generated fixing hints to improve all matched locations with identified patterns.
We identify most recent sources of transistor layout dependent effects (LDE) such as stress, lithography,
and well proximity effects (WPE), and outline modeling and analysis methods for 28 nm. These methods
apply to custom layout, standard cell designs, and context-aware post-route analysis. We show how IC
design teams can use a model-based approach to quantify and analyze variability induced by LDE. We
reduce the need for guard-bands that negate the performance advantages that stress brings to advanced
The impact of lithography-induced systematic variations on the parametric behavior of cells and chips designed on a TI
65nm process has been studied using software tools for silicon contour prediction, and design analysis from contours.
Using model-based litho and etch simulation at different process conditions, contours were generated for the poly and
active layers of standard cells in multiple contexts. Next, the extracted transistor-level SPICE netlists (with annotated
changes in CD) were simulated for cell delay and leakage. The silicon contours predicted by the model-based litho tools
were validated by comparing CDs of the simulated contours with SEM images. A comparative analysis of standard cells
with relaxed design rules and restricted pitch design rules showed that restrictive design rules help reduce the variation
from instance to instance of a given cell by as much as 15%, but at the expense of an area penalty. A full-chip variability
analysis flow, including model-based lithography and etch simulation, captures the systematic variability effects on
timing-critical paths and cells and allows for comparison of the variability of different cells and paths in the context of a
With increasing chip sizes and shrinking device dimensions, on-chip semiconductor process variation can no longer be
ignored in the design and signoff static timing analysis of integrated circuits. An important parameter affecting CMOS
technologies is the gate length (Lgate) of a transistor. In modern technologies, significant spatial intra-chip variability of
transistor gate lengths, which is systematic as opposed to random, can lead to relatively large variations in circuit path
delays. Spatial variations in Lgate affect circuit timing properties, which can lead to timing errors and performance loss.
To maximize performance and process utilization in microprocessor designs, we have developed and validated a timing
analysis methodology based on accurate silicon contour prediction from drawn layout and contour-based extraction of
our designs. This allows for signoff timing without unnecessarily large margins, thereby reducing chip area and
maximizing performance while ensuring chip functionality, improved process utilization and yield. In this paper, we
describe the chip timing methodology, its validation and implementation in microprocessor design.