Dr. Jac Paul Condella
OPC Engineer at Cadence Design Systems Inc
SPIE Involvement:
Author
Publications (4)

Proceedings Article | 23 March 2020 Presentation + Paper
Proc. SPIE. 11328, Design-Process-Technology Co-optimization for Manufacturability XIV
KEYWORDS: Metals, Silicon, Manufacturing, Reliability, Design for manufacturing, Extreme ultraviolet lithography, Optical proximity correction, Semiconducting wafers, Yield improvement, Chemical mechanical planarization

Proceedings Article | 5 April 2011 Paper
Proc. SPIE. 7974, Design for Manufacturability through Design-Process Integration V
KEYWORDS: Lithography, Statistical analysis, Data modeling, Calibration, Ions, Silicon, Transistors, Neodymium, Device simulation, Standards development

Proceedings Article | 19 March 2008 Paper
Proc. SPIE. 6925, Design for Manufacturability through Design-Process Integration II
KEYWORDS: Lithography, Data modeling, Etching, Silicon, Scanning electron microscopy, Transistors, Optical proximity correction, Critical dimension metrology, Model-based design, Process modeling

Proceedings Article | 4 March 2008 Paper
Proc. SPIE. 6925, Design for Manufacturability through Design-Process Integration II
KEYWORDS: Lithography, Clocks, Data modeling, Databases, Etching, Silicon, Shape analysis, Transistors, Optical proximity correction, Picosecond phenomena

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