Ms. Jae-Hyun Kang Profile

Jae-Hyun Kang

Senior Engineer at SAMSUNG Electronics Co Ltd

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Author

Publications (27)

Proceedings Article | 10 April 2024 Presentation + Paper

A new era DFM solution for yield enhancement using machine learning (ML)

Namjae Kim, Jae-Hyun Kang, SangWoo Jung, DaeHyun Jang, ByungMoo Kim, JoongWon Jeon, Ja-Hum Ku, Kareem Madkour, Joe Kwan

Proceedings Volume 12954, 1295411 (2024) https://doi.org/10.1117/12.3009798

KEYWORDS: Design for manufacturing, Design, Data modeling, Machine learning, Education and training, Yield improvement, Metals, Matrices, Cadmium, Reflection

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Proceedings Article | 23 March 2020 Presentation + Paper

Jaehwan Kim, Jin Kim, Byungchul Shin, Sangah Lee, Jae-Hyun Kang, Joong-Won Jeon, Piyush Pathak, Jac Condella, Frank Gennari, Philippe Hurat, Ya-Chieh Lai

Proceedings Volume 11328, 113280I (2020) https://doi.org/10.1117/12.2551970

KEYWORDS: Metals, Design for manufacturing, Chemical mechanical planarization, Silicon, Reliability, Optical proximity correction, Semiconducting wafers, Extreme ultraviolet lithography, Manufacturing, Yield improvement

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Proceedings Article | 4 April 2019 Presentation + Paper

A novel design-for-yield solution based on interconnect level layout improvements at 7nm technology node

Jaehwan Kim, Sangah Lee, Byungchul Shin, J. Jeon, Jin Kim, B. M. Kim, Jae-Hyun Kang, Seungweon Paek, Piyush Pathak, Frank Gennari, Philippe Hurat, Ya-Chieh Lai

Proceedings Volume 10962, 1096204 (2019) https://doi.org/10.1117/12.2514896

KEYWORDS: Computer aided design, Metals, Resolution enhancement technologies, Optical lithography, CMOS technology, Extreme ultraviolet, Extreme ultraviolet lithography, Lithography, Double patterning technology, Manufacturing

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Proceedings Article | 20 March 2019 Paper

Machine learning to improve accuracy of fast lithographic hotspot detection

NamJae Kim, Kiheung Park, Jiwon Oh, Sangwoo Jung, Sangah Lee, Jae-hyun Kang, Seung Weon Paek, Kareem Madkour, Wael ElManhawy, Aliaa Kabeel, Ahmed ElGhoroury, Marwa Shafee, Asmaa Rabie, Joe Kwan

Proceedings Volume 10962, 1096216 (2019) https://doi.org/10.1117/12.2515139

KEYWORDS: Machine learning, Data modeling, Lithography, Neural networks, Manufacturing, Computer simulations, Design for manufacturability, Design for manufacturing, Feature extraction, Electronics

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Proceedings Article | 18 March 2015 Paper

High coverage of litho hotspot detection by weak pattern scoring

Jinho Park, NamJae Kim, Jae-hyun Kang, Seung Weon Paek, Steve Kwon, Marwah Shafee, Kareem Madkour, Wael ElManhawy, Joe Kwan, Jean-Marie Brunet

Proceedings Volume 9427, 942703 (2015) https://doi.org/10.1117/12.2087473

KEYWORDS: Phase modulation, Lithography, Image classification, Library classification systems, Visualization, Process modeling, Design for manufacturing, Manufacturing, Yield improvement, Land mines

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Achieving lithographic printability at advanced nodes (14nm and beyond) can impose significant restrictions on physical design, including large numbers of complex design rule checks (DRC) and compute-intensive detailed process model checking. Early identifying of yield-limiter hotspots is essential for both foundries and designers to significantly improve process maturity. A real challenge is to scan the design space to identify hotspots, and decide the proper course of action regarding each hotspot. Building a scored pattern library with real candidates for hotspots for both foundries and designers is of great value. Foundries are looking for the most used patterns to optimize their technology for and identify patterns that should be forbidden, while designers are looking for the patterns that are sensitive to their neighboring context to perform lithographic simulation with their context to decide if they are hotspots or not.[1] In this paper we propose a framework to data mine designs to obtain set of representative patterns of each design, our aim is to sample the designs at locations that can be potential yield limiting. Though our aim is to keep the total number of patterns as small as possible to limit the complexity, still the designer is free to generate layouts results in several million of patterns that define the whole design space. In order to handle the large number of patterns that represent the design building block constructs, we need to prioritize the patterns according to their importance. The proposed pattern classification methodology depends on giving scores to each pattern according to the severity of hotspots they cause, the probability of their presence in the design and the likelihood of causing a hotspot. The paper also shows how the scoring scheme helps foundries to optimize their master pattern libraries and priorities their efforts in 14nm technology and beyond. Moreover, the paper demonstrates how the hotspot scoring helps in improving the runtime of lithographic simulation verification by identifying which patterns need to be optimized to correctly describe candidate hotspots, so that only potential problematic patterns are simulated.

Proceedings Article | 29 March 2013 Paper

Model based hint for litho hotspot fixing beyond 20nm node

Jae-Hyun Kang, Byung-Moo Kim, Naya Ha, Hung bok Choi , Kee sup Kim , Sarah Mohamed, Kareem Madkour, Wael ElManhawy, Evan Lee, Jean-Marie Brunet, Joe Kwan

Proceedings Volume 8684, 86840N (2013) https://doi.org/10.1117/12.2011619

KEYWORDS: Lithography, Double patterning technology, Design for manufacturing, Resolution enhancement technologies, Manufacturing, Bridges, Visualization, Design for manufacturability, Metals, Electronics

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Proceedings Article | 15 March 2012 Paper

Thickness-aware LFD for the hotspot detection induced by topology

Jae-Hyun Kang, Naya Ha, Joo-Hyun Park, Byung-Moo Kim, Seung Weon Paek, Hungbok Choi, Kee Sup Kim, Ahmed Mohy, Shady Abdelwahed, Mohamed Imam

Proceedings Volume 8327, 83270P (2012) https://doi.org/10.1117/12.917998

KEYWORDS: Semiconducting wafers, Metals, Process modeling, Image processing, Design for manufacturing, Chemical mechanical planarization, Optical proximity correction, 3D modeling, Photovoltaics, Scanning electron microscopy

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Proceedings Article | 15 March 2012 Paper

In-design process hotspot repair using pattern matching

Daehyun Jang, Naya Ha, Junsu Jeon, Jae-Hyun Kang, Seung Weon Paek, Hungbok Choi, Kee Sup Kim, Ya-Chieh Lai, Philippe Hurat, Wilbur Luo

Proceedings Volume 8327, 83270S (2012) https://doi.org/10.1117/12.916199

KEYWORDS: Silicon, Manufacturing, Lithography, Failure analysis, Data processing, Chemical mechanical planarization, Semiconducting wafers, Design for manufacturability, Tolerancing, Optical lithography

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Proceedings Article | 15 March 2012 Open Access

Yield enhancement with DFM

Seung Weon Paek, Jae Hyun Kang, Naya Ha, Byung-Moo Kim, Dae-Hyun Jang, Junsu Jeon, DaeWook Kim, Kun Young Chung, Sung-eun Yu, Joo Hyun Park, SangMin Bae, DongSup Song, WooYoung Noh, YoungDuck Kim, HyunSeok Song, HungBok Choi, Kee Sup Kim, Kyu-Myung Choi, Woonhyuk Choi, JoongWon Jeon, JinWoo Lee, Ki-Su Kim, SeongHo Park, No-Young Chung, KangDuck Lee, YoungKi Hong, BongSeok Kim

Proceedings Volume 8327, 832704 (2012) https://doi.org/10.1117/12.920029

KEYWORDS: Design for manufacturing, Silicon, Polishing, Optical proximity correction, Back end of line, Metals, Failure analysis, Yield improvement, Logic, Manufacturing

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Proceedings Article | 4 April 2011 Paper

A state-of-the-art hotspot recognition system for full chip verification with lithographic simulation

Mark Simmons, Jae-Hyun Kang, Youngkeun Kim, Joung Il Park, Seung weon Paek, Kee-sup Kim

Proceedings Volume 7974, 79740M (2011) https://doi.org/10.1117/12.881596

KEYWORDS: Computer aided design, Lithography, Semiconducting wafers, Device simulation, Design for manufacturing, Data modeling, Semiconductors, Manufacturing, Pattern recognition, Visualization

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In today's semiconductor industry, prior to wafer fabrication, it has become a desirable practice to scan layout designs for lithography-induced defects using advanced process window simulations in conjunction with corresponding manufacturing checks. This methodology has been proven to provide the highest level of accuracy when correlating systematic defects found on the wafer with those identified through simulation. To date, when directly applying this methodology at the full chip level, there has been unfavorable expenses incurred that are associated with simulation which are currently overshadowing its primary benefit of accuracy - namely, long runtimes and the requirement for an abundance of cpus. Considering the aforementioned, the industry has begun to lean towards a more practical application for hotspot identification that revolves around topological pattern recognition in an attempt to sidestep the simulation runtime. This solution can be much less costly when weighing against the negative runtime overhead of simulation. The apparent benefits of pattern matching are, however, counterbalanced with a fundamental concern regarding detection accuracy; topological pattern identification can only detect polygonal configurations, or some derivative of a configuration, which have been previously identified. It is evident that both systems have their strengths and their weaknesses, and that one system's strength is the other's weakness, and vice-versa. A novel hotspot detection methodology that utilizes pattern matching combined with lithographic simulation will be introduced. This system will attempt to minimize the negative aspects of both pattern matching and simulation. The proposed methodology has a high potential to decrease the amount of processing time spent during simulation, to relax the high cpu count requirement, and to maximize pattern matching accuracy by incorporating a multi-staged pattern matching flow prior to performing simulation on a reduced data set. Also brought forth will be an original methodology for constructing the core pattern set, or candidate hotspot library, in conjunction with establishing hotspot and coldspot pattern libraries. Lastly, it will be conveyed how this system can automatically improve its potential as more designs are passed through it.

Proceedings Article | 16 March 2009 Paper

Smart data filtering for enhancement of model accuracy

Shady Abdelwahed, Jae Hyun Kang, Jaeyoung Choi, Jong Doo Kim, Hyesung Lee, Sungho Jun, Youngmi Kim

Proceedings Volume 7274, 727423 (2009) https://doi.org/10.1117/12.814153

KEYWORDS: Calibration, Data modeling, Process modeling, Optical proximity correction, Lithography, Semiconducting wafers, Scanning electron microscopy, Photomasks, Image processing, Critical dimension metrology

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Proceedings Article | 16 March 2009 Paper

Pre-OPC layout decomposition for improved image fidelity

Shady Abdelwahed, Rami Fathy, Jae Hyun Kang, Jong Doo Kim, Youngmi Kim

Proceedings Volume 7274, 72742I (2009) https://doi.org/10.1117/12.816825

KEYWORDS: Optical proximity correction, Photomasks, Resolution enhancement technologies, Semiconducting wafers, Optical lithography, Lithography, Image processing, Manufacturing, Silicon, Microelectronics

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Proceedings Article | 17 October 2008 Paper

Combination of rule and pattern based lithography unfriendly pattern detection in OPC flow

Jae-Hyun Kang, Jae-Young Choi, Yeon-Ah Shim, Hye-Sung Lee, Bo Su, Walter Chan, Ping Zhang, Joanne Wu, Keun-Young Kim

Proceedings Volume 7122, 71221N (2008) https://doi.org/10.1117/12.801312

KEYWORDS: Optical proximity correction, Design for manufacturing, Lithography, Scanning electron microscopy, Detection and tracking algorithms, Databases, Bridges, Model-based design, Fuzzy logic, Defect detection

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Foundry companies encounter again and again the same or similar lithography unfriendly patterns (Hot-spots) in different designs within the same technology node and across different technology nodes, which eluded design rule check (DRC), but detected again and again in OPC verification step. Since Model-based OPC tool applies OPC on whole-chip design basis, individual hot-spot patterns are treated same as the rest of design patterns, regardless of its severity. We have developed a methodology to detect those frequently appeared hot-spots in pre-OPC design, as well as post OPC designs to separate them from the rest of designs, which provide the opportunity to treat them differently in early OPC flow. The methodology utilizes the combination of rule based and pattern based detection algorithms. Some hotspot patterns can be detected using rule-based algorithm, which offer the flexibility of detecting similar patterns within pre-defined ranges. However, not all patterns can be detected (or defined) by rules. Thus, a pattern-based approach is developed using defect pattern library concept. The GDS/OASIS format hot-spot patterns can be saved into a defect pattern library. Fast pattern matching algorithm is used to detect hot-spot patterns in a design using the library as a pattern template database. Even though the pattern matching approach lacks the flexibility to detect patterns' similarity, but it has the capability to detect any patterns as long as a template exists. The pattern-matching algorithm can be either exact match or a fuzzy match. The rule based and pattern based hot-spot pattern detection algorithms complement each other and offer both speed and flexibility in hot spot pattern detection in pre-OPC and post-OPC designs. In this paper, we will demonstrate the methodology in our OPC flow and the benefits of such methodology application in production environment for 90nm designs. After the hot spot pattern detection, examples of special treatment to selected hot spot patterns will be shown.

Proceedings Article | 1 November 2007 Paper

Application of modified jog-fill DRC rule on LFD OPC flow

Young-Mi Kim, Sang-Uk Lee, Jea-Hyun Kang, Jea-Hee Kim, Kee-Ho Kim

Proceedings Volume 6730, 67303W (2007) https://doi.org/10.1117/12.746811

KEYWORDS: Optical proximity correction, Semiconducting wafers, Lithography, Metals, Photomasks, Databases, Reticles, Optical lithography, Logic, Bridges

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Proceedings Article | 5 April 2007 Paper

Enhanced hole shape of flash devices in ArF lithography by eliptical mask bias technique

Young-Doo Jeon, Sungho Jun, Jae-Hyun Kang, Sang-Uk Lee, Jeahee Kim, Keeho Kim

Proceedings Volume 6518, 65183W (2007) https://doi.org/10.1117/12.712016

KEYWORDS: Photomasks, Optical proximity correction, Optical lithography, Lithography, Diffraction, Data modeling, Process modeling, Optical properties, Semiconductor manufacturing, Bridges

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Proceedings Article | 4 April 2007 Paper

Methodology to set up accurate OPC model using optical CD metrology and atomic force microscopy

Yeon-Ah Shim, Jaehyun Kang, Sang-Uk Lee, Jeahee Kim, Keeho Kim

Proceedings Volume 6518, 65180C (2007) https://doi.org/10.1117/12.711936

KEYWORDS: Data modeling, Critical dimension metrology, Optical proximity correction, Atomic force microscopy, Scanning electron microscopy, Semiconducting wafers, Wafer-level optics, Statistical modeling, Electron beams, Metrology

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Proceedings Article | 27 March 2007 Paper

Advanced new OPC method to improve OPC accuracy for sub-90-nm technology

Jaeyoung Choi, Jaehyun Kang, Yeonah Shim, Kyunghee Yun, Jiho Hong, Yongseok Lee, Keeho Kim

Proceedings Volume 6520, 652047 (2007) https://doi.org/10.1117/12.712001

KEYWORDS: Data modeling, Optical proximity correction, Data conversion, Process modeling, Critical dimension metrology, Reactive ion etching, Scanning electron microscopy, Photomasks, Etching, Image processing

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Proceedings Article | 21 March 2007 Paper

Application of enhanced dynamic fragmentation to minimize false error from post OPC verification

Jae-Hyun Kang, Sang uk Lee, Jeahee Kim, Keeho Kim

Proceedings Volume 6521, 65210U (2007) https://doi.org/10.1117/12.711950

KEYWORDS: Optical proximity correction, Bridges, Model-based design, Photomasks, Neodymium, Lithography, Data modeling, System on a chip, Logic devices, Process modeling

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Proceedings Article | 20 October 2006 Paper

The effect of sub-layer condition on the OPC model

Jaeyoung Choi, Jaehyun Kang, Yeonah Shim, Kyunghee Yun, Junseok Lee, Yongseok Lee, Keeho Kim

Proceedings Volume 6349, 63494O (2006) https://doi.org/10.1117/12.686653

KEYWORDS: Data modeling, Optical proximity correction, Statistical modeling, Critical dimension metrology, Process modeling, Lithography, Scanners, Photoresist materials, Photoresist processing, Optimization (mathematics)

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Proceedings Article | 20 October 2006 Paper

Efficient approach to improving pattern fidelity with multi-OPC model and recipe

Munhoe Do, Jaehyun Kang, Jaeyoung Choi, Junseok Lee, Yongsuk Lee, Keeho Kim

Proceedings Volume 6349, 63494P (2006) https://doi.org/10.1117/12.686655

KEYWORDS: Optical proximity correction, Logic, Databases, System on a chip, Data modeling, Photomasks, Instrument modeling, Manufacturing, Electronics, Distortion

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Proceedings Article | 20 May 2006 Paper

A study for effect of rounded contact hole pattern by laser mask writing machine onto wafer process margin

Se-Jin Park, Kyung-Hee Yoon, Jae-Hyun Kang, Jae-Young Choi, Yong-Suk Lee, Keeho Kim

Proceedings Volume 6283, 62831K (2006) https://doi.org/10.1117/12.681745

KEYWORDS: Photomasks, Semiconducting wafers, Deep ultraviolet, Lithography, Laser systems engineering, Electron beam lithography, Critical dimension metrology, Scanners, Back end of line, Data modeling

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Proceedings Article | 20 March 2006 Paper

Simulation based post OPC verification to enhance process window, critical failure analysis, and yield

Jae-Hyun Kang, Jae-Young Choi, Kyung-Hee Yun, Munho Do, Yong-Suk Lee, Keeho Kim

Proceedings Volume 6154, 61543J (2006) https://doi.org/10.1117/12.657050

KEYWORDS: Optical proximity correction, Process modeling, Critical dimension metrology, Photomasks, Bridges, Lithography, Semiconducting wafers, Failure analysis, Data modeling, Scanning electron microscopy

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Proceedings Article | 20 March 2006 Paper

Mask process variation induced OPC accuracy in sub-90nm technology node

Se-Jin Park, Yeon-Ah Shim, Jae-Hyun Kang, Jae-Young Choi, Kyung-Hee Yoon, Yong-Suk Lee, Keeho Kim

Proceedings Volume 6154, 61543K (2006) https://doi.org/10.1117/12.657036

KEYWORDS: Photomasks, Optical proximity correction, Semiconducting wafers, Electroluminescence, Critical dimension metrology, Lithography, Data modeling, Error analysis, Logic, Etching

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Proceedings Article | 12 May 2005 Paper

Modified optical proximity correction model to compensate pattern density induced optical proximity effect

Jaehyun Kang, Juhyun Kim, Sukwon Jung, Honglae Kim, Keeho Kim

Proceedings Volume 5754, (2005) https://doi.org/10.1117/12.601420

KEYWORDS: Optical proximity correction, Etching, Lithography, Image processing, Semiconducting wafers, Critical dimension metrology, Data modeling, Process modeling, Instrument modeling, Scanning electron microscopy

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Proceedings Article | 12 June 2003 Paper

Investigation on the role of residual casting solvent in photolithographic behavior in 193-nm resists

Jae-Hyun Kang, Seung-Keun Oh, Eun-Kyung Son, Jung-Woo Kim, Yun-Hyi Kim, Yong-Jun Choi, Deog-Bae Kim, Jaehyun Kim

Proceedings Volume 5039, (2003) https://doi.org/10.1117/12.485163

KEYWORDS: Diffusion, Electroluminescence, Polymers, Polymer thin films, Lithography, Semiconducting wafers, Silicon films, Molecules, Silicon, Chemically amplified resists

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Proceedings Article | 2 June 2003 Paper

Atomic force microscopy of steep side-walled feature with carbon nanotube tip

Byong Chon Park, Jae-Hyun Kang, Ki Jung, Won Young Song, Beomhoan O, TaeBong Eom

Proceedings Volume 5038, (2003) https://doi.org/10.1117/12.482816

KEYWORDS: Atomic force microscopy, Carbon nanotubes, Silicon, Critical dimension metrology, Silicon carbide, Adsorption, Metrology, Positive feedback, Computer engineering, Carbon

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Proceedings Article | 24 July 2002 Paper

Macrocycle monomer having ethyleneoxy unit to buffer acid diffusion (new base for photoresist)

Geunsu Lee, Keun-Kyu Kong, Jae Chang Jung, Ki-Soo Shin, Jae-Hyun Kang, Sang-Don Kim, Yong-Jun Choi, Se-Jin Choi, Deog-Bae Kim, Jae-Hyun Kim

Proceedings Volume 4690, (2002) https://doi.org/10.1117/12.474211

KEYWORDS: Photoresist materials, Polymers, Diffusion, Line edge roughness, Contamination, Ions, Hydrogen, Photoresist developing, Etching, Lithography

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Showing 5 of 27 publications

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