Imec logic N2+ design rule defines a minimum via pitch of 36nm. An EUV single patterning solution at 0.33 NA is explored on a random logic via design. From an earlier simulation study , it was shown that Ta-based bright field mask delivers the best resolution enhancement technology (RET) solution. In this paper the simulation results will be validated on wafer. Negative-tone development (NTD) with a metal-oxide resist process using a bright field (BF) mask and positivetone development (PTD) with a chemically amplified resist process using a dark field (DF) mask are compared. In addition, source-mask optimizations (SMO) including sub-resolution assist features (SRAF) were used as a RET, and optical proximity correction (OPC) was carried out on the design clips to achieve optimum lithography performance. We report the best choice among the listed options, and present our recommendation on OPC, RET and process based on the simulation and wafer data in order to improve the resolution, therefore extending the single exposure pitch limit.
To maintain good critical dimension control, optical proximity correction (OPC) has relied on fast compact models to capture the underlying lithography process in advanced nodes. Compact models have always been deterministic in the sense that they predict the average dimensions or contours on wafer. With the introduction of extreme ultraviolet (EUV) lithography, this approach breaks down due to large variabilities in EUV lithography processes. Recently, empirical correlations were found between this variability and imaging metrics, allowing the development of compact models. Such stochastic models have been used successfully to predict hotspots. In this paper an attempt is made to apply such stochastic models during OPC to reduce the number of stochastic failures. Different OPC strategies are applied on an advanced random logic and SRAM design, focusing on a via layer with a calibrated stochastic model. Through simulations, we show that the failure rate can be reduced by using a stochastic model during OPC, at the expense of edge placement error. However, when reducing the stochastic band width to match the process variation band width, no meaningful differences were observed between process-window OPC and stochastic OPC due to uniformity of pattern dimensions in sample layout.
Directed self-assembly (DSA) process has been introduced and developed for more than a decade as one of the alternative advanced patterning techniques in the semiconductor industry. Block copolymer (BCP) is self-assembling into the desired pattern on the lithographically defined pre-pattern on the wafer. Such a bottom-up approach is used to define the pattern which is typically hard to achieve with the traditional top-down approach. As an example, the density of the pattern can be increased with DSA by the factor of 3 or 4 from the 193i lithography pattern. Although similar dimension becomes now accessible with EUV lithography, DSA keeps its benefit; the structure is simply defined by the phase separation of materials rather than the complex light-matter interactions as required for EUV resist patterning. In this presentation, we will discuss the synergetic impact of the combination of EUV and DSA.
According to the Power-Performance-Area requirements in advanced technology node, we already scaled down poly pitch (CPP) and metal pitch (MP) which considered as main factors to form standard cell (SDC) area. However, in recent technology nodes, the scaling of CPP and MP started to slow down, due to the physical limitation. To continue to meet the requirements, combined with Design-Technology co-optimization (DTCO), the height of standard cell would become the main factor here, which we could reduce it by reducing the number of tracks. In this paper, we would introduce 3DIC as one of the design options for 2nm node to keep scaling by reducing the cell height with its specific 3D structure and inserted booster. Also, we would introduce the coming challenges as importing 3D-IC to 2nm technology node.
Imec N3 logic design rules define a minimum via pitch of 36nm for a double patterning process. Enabling this pitch is crucial in terms of process time and number of masks involved. One method for extending 0.33 NA EUV is using advanced mask materials. Studies have shown that a low-n attenuated phase-shift mask (PSM) can improve EUV imaging performance, reduce mask 3D effects and improve optical contrast compared to the reference Ta-based mask. [1-3] In this paper, the impact of mask stack - Ta-based (binary or BIM) and low-n (PSM) - and mask tone - dark field (DF) vs. bright field (BF) - on a random logic Via layer will be evaluated. To pattern contact holes, we use negative tone development (NTD) metal-oxide resist process using the BF mask and positive tone development (PTD) chemically amplified resist process using the DF mask. Source mask optimization (SMO) was performed with and without subresolution assist feature (SRAF) as a resolution enhancement technology (RET). Optical proximity correction (OPC) was carried out on design clips using respective sources and mask rules at different mask tone. We show the optimum choice for this layer and present our recommendation based on current OPC simulations as well as some preliminary wafer data.
Design rule for advanced logic node is optimized together with EUV NXE 3400 wafer data and OPC performance. Imaging parameters such as SMO source, dose sensitivity, MEEF and other are considered in defining the pattern fidelity and associated design rules. In addition, positive tone development (PTD) process employing Dark Field (DF) EUV mask and negative tone development (NTD) process using Bright Field (BF) mask are included in the scope. Key differences between PTD and NTD process will be discussed from the perspective of fundamental imaging, OPC and lithography process. At last, stochastic effect will be evaluated on the key design rules such as tip- to-tip, tip-to-line, width/space etc.
In this work we are introducing a manufacturing flow for the SALELE Process in details. Starting with layout decomposition, where the drawn layer is decomposed into 4 Masks: 2 Metal-like Masks, and 2 Block-like Masks. Then each of these masks is subjected to Optical Proximity Correction (OPC) process, and here we explain more about the OPC recipe development for each mask. Then we introduce a verification flow that performs two levels of verifications: (a) Litho verification, where the litho fidelity of each mask is quantified based on image quality measurements. (b) Final Manufactured shapes verification vs. expected output. This work has been carried out on an N3 candidate layout designed by IMEC.
Self-aligned quadruple patterning (SAQP) is not compatible with every design. It couldn’t pattern even number routing track, for examples 4 internal routing tracks with power rails side by side, due to the process footprint of conventional SAQP. On the other hand SAQP spacer merge technique is able to remove 1 internal metal line by merging 2 spacer into 1 spacer. It can offer additional track scaling and flexible design of track number, for example, 5.5 tracks together with 6.5 tracks to accomplish low and high performance device respectively. In this paper, SAQP spacer merge technique and self-aligned block (SAB) process are considered as one of potential patterning approaches for 1D style 28 nm metal pitch. SAQP spacer merge technique is indispensable for supporting 5.5T cell of 4 internal tracks with 28nm metal pitch. And 5.5T cell also requires the irregular metal color array for SAB and its biases which is litho-etch skew. SAB can be sized up double compared to conventional block process, it is biased over next metal line to takes advantage of material etch selectivity of SAQP structure inherently before metallization. To meets those requirement with automatic mask layout generation, we newly proposed forward decomposition algorithm and color-aware block resizing of SAB. The forward decomposition algorithm generates mandrel to spacer 1 to spacer 2 to mimics process order of SAQP spacer merge technique. And color-aware block resizing of SAB needs conditional bias depending on neighboring metal color. Additionally, edge placement error budget is analyzed with process variation band of source mask optimization (SMO) on top of overlay, line edge roughness (LER) and etch uniformity assumption. Simulation result seems to be fine to enable SAQP spacer merge and SAB integration. However, EUV stochastics reported that CD uniformity is not fit in Gaussian distribution. Considering beyond 3σ, restricted design rule may be needed. To see design availability, 3 representative standard library cells were verified in design rule restriction without area loss. This SAQP spacer merge decomposition algorithm is useful since it is possible to extend for Fin patterning application as well.
In the early 2000s, membranes both thin enough to transmit EUV light and strong enough to be free-standing at mask dimensions did not exist. The lithography community assumed that defect control for photomasks would be achieved, not with a pellicle, but with a clean scanner environment, thermophoretic protection and a removable pellicle.1 In 2006, Intel published their research on an EUV pellicle.2 Since then, an international development effort on EUV pellicle membranes has spanned a range of materials and fabrication approaches. Not only materials, but also the requirements of the EUV pellicle membrane have evolved over time. Imec’s pellicle work based on carbon nanotubes (CNTs) started in 2015, and is placed in relation to the rich history of EUV pellicles. CNTs are one-atom-thick carbon sheets rolled into tubes. The CNTs can be single- or multi-walled and can vary in diameter and in length. These engineered CNTs can be arranged in different configurations to form membranes of different densities. Thus, the CNT membrane’s properties can be fundamentally changed to meet the EUV pellicle targets for properties like transmittance. The historical trends in EUV pellicle membrane development are presented and the CNT membranes are described in that context.
KEYWORDS: Optical lithography, Extreme ultraviolet, Metals, Logic, Manufacturing, Lithography, Back end of line, Extreme ultraviolet lithography, New and emerging technologies
In order to maintain the scaling trend in logic technology node progression, imec technology nodes started heavily utilizing design technology co-optimization (DTCO) on top of loosen pitch scaling trend to mitigate the burden from steep cost increase and yield challenge. Scaling boosters are adopted to enable DTCO process on top of patterning near its cliff to mitigate the cost increase. As the technology node further proceeds, DTCO also starts facing its cliff, and system technology co-optimization (STCO) is introduced to assist pitch and DTCO scaling to bridge 2-D IC technology to evolutionary technology options such as MRAM, 2.5-D heterogeneous integration, 3-D integration and 3-D IC. EUV is used to further assist pitch and DTCO scaling to maintain low cost with higher yield and faster turn-around-time (TAT). EUV single patterning, multiple patterning and high-NA EUV are considered on top of DTCO and STCO landscape to define imec technology nodes.
imec’s investigation on EUV single patterning insertion into industry 5nm-relevant logic metal layer is discussed. Achievement and challenge across imaging, OPC, mask data preparation and resulting wafer pattern fidelity are reported with a broad scope.
Best focus shift by mask 3D of isolated feature gets worse by the insertion of SRAF, which puts a negative impact on obtaining large overlap process window across features. imec’s effort across OPC including SMO and mask sizing is discussed with mask rule that affects mask writing. Resist stochastic induced defect is identified as a biggest challenge during the overall optimization, and options to overcome the challenge is investigated. For mask data preparation, dramatic increase in the data volume in EUV mask manufacturing is observed from iArF multiple patterning to EUV single patterning conversion, particularly by the insertion of SRAF. In addition, logic design consideration to make EUV single patterning more affordable compared to alternative patterning option is be discussed.
Conventional via patterning which relies on immersion ArF (iArF) lithography and self-aligned via (SAV) becomes
challenging in sub-7nm technology. EUV lithography (EUVL) is expected to achieve smaller feature
patterning thanks to its short wave length, but edge placement error (EPE) margin remains as another bottleneck
of pitch scaling; SAV can be aligned with metal on the top but not with the bottom of the via. Literary
study shows previous work on 2D self-aligned via (2D SAV) which can be aligned with the both metals, but it
cannot extend technology scaling beyond sub-5nm whose minimum metal pitch is expected as sub-20nm due to
essential limitation of EPE margin. We propose large marginal 2D SAV which has three times large EPE margin
than normal 2D SAV for extremely shrunk technology node (e.g. sub-5nm). Large marginal 2D SAV may allow
further feature size scaling, but it requires four EUV masks. Therefore, we present two count reduction methods
and corresponding mask decompositions and pattern re-targetings. Proposed re-targeted patterns are assessed
by source mask optimization (SMO) in terms of maximum EPE and process variation band (PVB) width.
EUV lithography (EUVL) is rising up as a solution of sub-10nm technology node via patterning. Due to better resolution of EUVL than it of immersion ArF (iArF) lithography, multiple iArF masks can be replaced by one EUV mask. However, for 24nm by 24nm metal grid, two diagonally neighboring vias yield either contour of two holes or peanut-shape contour. Because of the large variability of the via contours, the two vias are separably patterned with two different masks. We propose to insert bridge patterns (BPs) at the middle of the diagonally neighboring vias, so that single EUV exposure can draw peanut-shape contour consistently. In this study, we also assume 2D self-aligned via (2D SAV) which can align via holes in both vertical and horizontal direction for better edge placement error margin, so unique re-targeted via patterns that is called bridged via (BV) appears. We investigate impact of BV size and BP shapes on simulated contour using source mask optimization, and popular BVs are compared in terms of probability of failure which are calculated with Monte-Carlo simulation.
A protective membrane – a pellicle – must be used to prevent yield loss during EUV lithography exposure, just as it was for 193nm lithography. The pellicle must be thin enough to transmit EUV light, yet strong enough to withstand the scanner environment. Membrane solutions for ~ 80W exposure exist. Our focus is developing a membrane solution for 250W exposure power. The main pellicle challenge here is still the identification of a membrane material that has very high transmission at EUV wavelengths. Additionally, absorption during lithographic exposure results in high thermal and mechanical load for the pellicle, which can cause yield problems. The current candidates for pellicle membranes such as poly-silicon and silicon nitride cannot withstand 250W power conditions, therefore alternative materials will be required for the future HVM pellicle.
At imec, a variety of novel membrane material options are investigated for the HVM pellicle application. One promising approach is based on carbon nanotubes (CNT). In this paper we outline different CNT based process options, and report results on their optical, thermal, and mechanical performance. In addition, we will report on their uniformity and robustness towards scanner application. Finally, the family of CNT-based membrane options will be compared to promising candidates fabricated using conventional film approaches that do not have a CNT layer.
EUV lithography insertion is anticipated at the 7 nm node and below; however, defects added to the mask during use is a
lingering concern. Defectivity in the scanner is non-zero and an EUV pellicle membrane to protect the mask for high
volume manufacturing power levels does not yet exist. The EUV photons are strongly absorbed by all materials. Sibased
membranes leverage the low absorption coefficient k value (k = 0.0018 at 13.5 nm) for reasonable transmission,
but poly Si becomes fragile and wrinkles during the high temperatures associated with exposure. An alternate approach
to high transmission is deploying very thin or porous layers so that there are fewer atoms to absorb light. For example,
carbon nanomaterials have a reasonably low k value (k = 0.0069), but are strong enough to be fabricated in very thin
layers. Graphene, graphite, carbon-nanosheets and carbon nanotubes are all candidate carbon nanomaterials for this
application, but we focus here on carbon nanotubes (CNTs). Our first measurements on CNT films of ~60 nm thick were
found to have 96.5% transmission at 13.5 nm. Adding CNT layers also enhanced the strength of a thin SiN membrane
significantly. In this paper, critical pellicle metrics will be evaluated in more detail: EUV transmission, bulge test for
mechanical strength, emissivity measurements for heat management, and exposure testing in a hydrogen environment.
EUV mask protection against defects during use remains a challenge for EUV lithography. A stand-off protective membrane – a pellicle – is targeted to prevent yield losses in high volume manufacturing during handling and exposure, just as it is for 193nm lithography. The pellicle is thin enough to transmit EUV exposure light, yet strong enough to remain intact and hold any particles out of focus during exposure. The development of pellicles for EUV is much more challenging than for 193nm lithography for multiple reasons including: high absorption of most materials at EUV wavelength, pump-down sequences in the EUV vacuum system, and exposure to high intensity EUV light. To solve the problems of transmission and film durability, various options have been explored. In most cases a thin core film is considered, since the deposition process for this is well established and because it is the simplest option. The transmission specification typically dictates that membranes are very thin (~50nm or less), which makes both fabrication and film mechanical integrity difficult. As an alternative, low density films (e.g. including porosity) will allow thicker membranes for a given transmission specification, which is likely to improve film durability. The risk is that the porosity could influence the imaging. At imec, two cases of pellicle concepts based on reducing density have been assessed : (1) 3D-patterned SiN by directed self-assembly (DSA), and (2) carbon nanomaterials such as carbon nanotubes (CNT) and carbon nanosheets (CNS). The first case is based on SiN membranes that are 3D-patterned by Directed Self Assembly (DSA). The materials are tested relative to the primary specifications: EUV transmission and film durability. A risk assessment of printing performance is provided based on simulations of scattered energy. General conclusions on the efficacy of various approaches will provided.
EUV mask protection during handling and exposure remains a challenge for high volume manufacturing using EUV scanners. A thin, transparent membrane can be mounted above the mask pattern so that any particle that falls onto the front of the mask is held out of focus and does not image. The fluoropolymer membranes that are compatible with 193nm lithography absorb too strongly at the 13.5nm EUV exposure wavelength to be considered. Initially, the industry planned to expose EUV masks without any pellicle; however, the time and cost of fabricating and qualifying an EUV mask is simply too high to risk decimating wafer yield each time a particle falls onto the mask pattern. Despite the challenges of identifying a membrane for EUV, the industry has returned to the pellicle concept for protection. EUVL pellicles have been in development for more than a decade and reasonable options exist. Meeting all pellicle requirements is difficult, so this type of risk-mitigation effort is needed to ensure that there is a viable high-volume manufacturing option. This paper first reviews the desired membrane properties for EUVL pellicles. Next, candidate materials are introduced based on reported properties and compatibility with fabrication. Finally a set of candidate membranes are fabricated. These membranes are screened using a simplified set of tests to assess their suitability as an EUV pellicle. EUV transmission, film stress, and film durability data are included. The results are presented along with general guidelines for pellicle membrane properties for EUV manufacturing.
The resist underlayer (UL) has been shown to beneficially impact the exposure latitude in photolithography techniques.
As a result, the development of the resist UL is in progress for extreme ultraviolet lithography (EUVL) as well. Since the
aspect ratio of patterns increases as the feature size decreases, a high-performance EUV UL is expected to be in high
demand.
In this study, we evaluated the optical properties of the EUV UL by using the lithography simulation tool PROLITH X5
(KLA-Tencor). We quantified the imaging properties of a 14 nm half-pitch (HP) line and space (L/S) pattern by varying
the refractive index, extinction coefficient and thickness of the UL under 0.5 numerical aperture (NA) conditions with a
conventional binary intensity mask.
These simulations reveal that the number of photons absorbed in the photoresist increases as the refractive index of the
UL decreases; this results from the increase in reflectivity from the UL/photoresist interface. Therefore, the line critical
dimension (CD) mean value decreases and stochastic imaging properties improve in the observation plane. As the
refractive index of the UL is reduced, however, the light intensity in resist and the distribution of photons is distorted by
the standing wave effect, resulting in roughness and non-uniformity in the pattern sidewall. Therefore, the refractive
index of the UL should be similar to that of the photoresist in order to get the optimized performance.
The half-tone phase shift mask (PSM) has been suggested for better imaging performances like image contrast,
NILS and H-V bias compared to the binary mask (BIM) in EUV lithography. In this paper, we measured
imaging performance of a fabricated half-tone attenuated PSM with Coherent Scattering Microscopy (CSM) and
the results were compared with simulation data obtained by EM-suite tool. We prepared a half-tone attenuated
PSM which has 12.7% reflectivity and 180° phase shift with absorber stack of 16.5mn-thick TaN absorber and
24nm-thick Mo phase shifter. With CSM, an actinic inspection tool, we measured the imaging properties of
PSM. The diffraction efficiencies of BIM were measured as 31%, 36%, and 44% for 88 nm, 100 nm, and 128
nm mask CD, respectively, while those of PSM were measured as 45%, 62%, and 81%. Also the aerial image at
wafer level obtained by CSM with high volume manufacturing tool’s (HVM) illumination condition (NA=0.33,
σ=0.9) showed higher image contrast and NILS with phase shift effect. And the measured data were consistent
with the simulation data.
In EUV Lithography, mask shadowing effect and photon shot noise effect are the main sources of patterning limit,
critical dimension (CD) non-uniformity and low imaging properties. In this paper, the patterning performance of a 6%
attenuated phase shift mask (PSM) is valuated, and the results show that this can be used for half-pitch (hp) down to 14 nm with 0.33NA due to the improved stochastic patterning properties. The proposed PSM consists of 26.5 nm of TaN as an absorber layer and 14 nm of Mo as a phase shifter on 2.5 nm thick Ru capped Mo/Si multilayers. This structure has ~6% reflectivity at the absorber stack and 180° phase shift. The improved stochastic resist patterning properties of PSM were compared with those of conventional binary intensity mask (BIM) with a 70 nm-thick TaN absorber for the 14 ~ 22 nm line and space (L/S) 1:1 dense pattern with 0.33NA off-axis illumination conditions with a EUV generic resist model.
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