Introduction and problem statement
Given that EUV lithography allows printing smaller Critical Dimension (CD) features, it can result in non-normal distributed CD populations on ADI wafers [Civay SPIE AL 2014], leading to errors in predicted failure rates [Bristol SPIE AL 2017]. As a result, there is a need to quantify the actual behavior of the CD population extremes by means of massive metrology [Dillen EUVL 2018]. Not only allows this to study the CD distribution, we can in parallel also evaluate pattern quality and the failure mechanisms leading to defects. This massive metrology method provides an accurate failure rate based on CD, and enables new possibilities to define a failure rate based on different metrics in a single measurement.
We analyze the CD uniformity of pillars in polar coordinates using a global waveform based thresholding strategy. In conjunction with this CD information, we also evaluated the print quality of each individual measured feature.
Fig 1. In line detected anomalies and failure definitions
As we gather this information during the measurement of CD, we can limit the additional measurement overhead to neglectable levels.
Application and outlook
We will show how we can leverage this to determine a defect based process window and relations of failure mechanisms through process conditions (see figure 2). When we take failures in a CH dataset into account, we illustrate the effect on the shape of a large dataset distribution in figure 3.
Fig 2. Defect identification for a through exposure dose experiment of pillars. For each condition >13k pillars where measured. The plot clearly shows an asymmetric behavior due to different failure mechanisms at low and high energy. The 2 vertical lines at relative energies 0.93 and 1.05 times nominal indicate the low defect process window.
Fig 3. A distribution of measured regular grid dense CH. The red line is the unfiltered CD data, the blue line is the shape of the distribution after filtering individual CH measurements that have a much lower contrast than expected.
Many different advanced devices and design layers currently employ double patterning technology (DPT) as a means to overcome lithographic and OPC limitations at low k1 values. Certainly device layers with k1 value below 0.25 require DPT or other pitch splitting methodologies. DPT has also been used to improve patterning of certain device layers with k1 values slightly above 0.25, due to the difficulty of achieving sufficient pattern fidelity with only a single exposure. Unfortunately, this broad adoption of DPT also came with a significant increase in patterning process cost. In this paper, we discuss the development of a single patterning technology process using an integrated Inverse Lithography Technology (ILT) flow for mask synthesis. A single pattering technology flow will reduce the manufacturing cost for a k1 > 0.25 full chip random contact layer in a memory device by replacing the more expensive DPT process with ILT flow, while also maintaining good lithographic production quality and manufacturable OPC/RET production metrics.
This new integrated flow consists of applying ILT to the difficult core region and traditional rule-based assist features (RBAFs) with OPC to the peripheral region of a DRAM contact layer. Comparisons of wafer results between the ILT process and the non-ILT process showed the lithographic benefits of ILT and its ability to enable a robust single patterning process for this low-k1 device layer. Advanced modeling with a negative tone develop (NTD) process achieved the accuracy levels needed for ILT to control feature shapes through dose and focus. Details of these afore mentioned results will be described in the paper.
Aberration sensitivity matching between overlay metrology targets and the device cell pattern has become a common requirement on the latest DRAM process nodes. While the extreme illumination modes used demand that the delta in aberration sensitivity must be optimized, it is effectively limited by the ability to print an optimum target that will meet detectability and accuracy requirements. Therefore, advanced OPC techniques are required to ensure printability and have optimal detectability performance while maintaining sufficient process window to avoid patterning or defectivity issues.
In this paper, we have compared various mark designs with real cell in terms of aberration sensitivity under the specific illumination condition. The specific illumination model was used for aberration sensitivity simulation while varying mask tones and target designs. Then, diffraction based simulation was conducted to analyze the effect of aberration sensitivity on the actual overlay values. The simulation results were confirmed by comparing the OL results obtained by diffraction based metrology with the cell level OL values obtained using Critical Dimension Scanning Electron Microscope.