In this paper we discuss the mechanism by which process variations determine the overlay accuracy of optical metrology. We start by focusing on scatterometry, and showing that the underlying physics of this mechanism involves interference effects between cavity modes that travel between the upper and lower gratings in the scatterometry target. A direct result is the behavior of accuracy as a function of wavelength, and the existence of relatively well defined spectral regimes in which the overlay accuracy and process robustness degrades (`resonant regimes’). These resonances are separated by wavelength regions in which the overlay accuracy is better and independent of wavelength (we term these `flat regions’). The combination of flat and resonant regions forms a spectral signature which is unique to each overlay alignment and carries certain universal features with respect to different types of process variations. We term this signature the `landscape’, and discuss its universality. Next, we show how to characterize overlay performance with a finite set of metrics that are available on the fly, and that are derived from the angular behavior of the signal and the way it flags resonances. These metrics are used to guarantee the selection of accurate recipes and targets for the metrology tool, and for process control with the overlay tool. We end with comments on the similarity of imaging overlay to scatterometry overlay, and on the way that pupil overlay scatterometry and field overlay scatterometry differ from an accuracy perspective.
As the cost of manufacturing high-end semiconductors continues to increase, the value of combining and streamlining
metrology steps also increases. The two critical metrology steps for litho control are 1) overlay and 2) CD. In this study,
the authors demonstrate the capability of just such a combination CD and Overlay metrology solution to improve not
only the cost of manufacturing but also the quality of data and information feedback for better scanner control in high
volume production.
The authors demonstrate how using imaging and scatterometry technology on a single platform can provide a
comprehensive litho control solution for both CD and overlay in the litho module. In the study, the authors will use full
stack wafers from an advanced process node running in high volume manufacturing. Specifically, data will be generated
using PROLITH for lithographic simulations for optimal target designs and then empirical data will be collected using
the Archer 300 LCM from which optimal target selection and system performance will be determined and validated on
wafers using this advanced process technology.
Overlay continues to be one of the key challenges for photolithography in semiconductor manufacturing. It becomes
even more challenging due to the continued shrinking of the device node. The corresponding tighter overlay specs
require the consideration of new paradigms for overlay control, such as high-order control schemes and/or field-by-field
overlay control. These approaches have been demonstrated to provide tighter overlay control for design rule structures,
and can be applied to areas such as double patterning lithography (DPL), as well as for correcting non-linear overlay
deformation signatures caused by non-lithographic wafer processing. Previously we presented a study of high-order
control applied to high order scanner correction, high order scanner alignment, and the sampling required to support
these techniques. Here we extend this work, using sources of variation (SOV) techniques, and have further studied the
impact of field by field compensation. This report will show an optimized procedure for high order control using
production wafers and field by field control.
Traditional "matching matrix" methods for characterizing scanner matching assume that the scanner distortion
performance is static. The latest scanner models can adjust the distortion performance dynamically, at run-time. The
Scanner Match Maker (SMM) system facilitates calculation and application of these run-time adjustments, improving
effective overlay performance of the scanner fleet, allowing more flexibility for mix-and-match exposure. The overlay
|mean|+3s performance was improved significantly for a layer pair that is currently allowed mix-and-match pairing.
The tight overlay budgets required for 45nm and beyond make overlay control a very important topic. With the adoption
of immersion lithography, the incremental complexity brings much more difficulty to analyzing the source of variation
and optimizing the sampling strategy. In this paper, there will be a discussion about how the use of an advanced
sampling methodology and strategy can help to overcome this overlay control problem and insure sufficient overlay
information to be captured for effective production lot excursion detection as well as rework decision making. There
will also be a demonstration of the different correction methodologies to improve overlay control for dual-stage systems
in order to maximize the productivity benef its with minimal impact to overlay performance.
Overlay control is gaining more attention in recent years as technology moves into the 32nm era. Strict overlay
requirements are being driven not only by the process node but also the process techniques required to meet the design
requirements. Double patterning lithography and spacer pitch splitting techniques are driving innovative thinking with
respect to overlay control. As lithographers push the current capabilities of their 193nm immersion exposure tools they
are utilizing newly enabled control 'knobs'. 'Knobs' are defined as the adjustment points that add new degrees of
freedom for lithographers to control the scanner. Expanded control is required as current scanner capabilities are at best
marginal in meeting the performance requirements to support the ever demanding process nodes. This abstract is an
extension of the SPIE 2008 paper in which we performed thorough sources of variance analysis to provide insight as to
the benefits of utilizing high order scanner control knobs [1]. The extension this year is to expand the modeling
strategies and to validate the benefit through carefully designed experiments. The expanded modeling characterization
will explore not only high order correction capabilities but also characterize the use of field by field corrections as a
means to improve the overlay performance of the latest generation of immersion lithography tools. We will explore
various correction strategies for both grid and field modeling using KT AnalyzerTM.
Overlay metrology and control have been critical for successful advanced microlithography for many years, and are
taking on an even more important role as time goes on. Due to throughput constraints it is necessary to sample only a
small subset of overlay metrology marks, and typical sample plans are static over time. Standard production monitoring
and control involves measuring sufficient samples to calculate up to 6 linear correctables. As design rules shrink and
processing becomes more complex, however, it is necessary to consider higher order modeled terms for control, fault
detection, and disposition. This in turn, requires a higher level of sampling. Due to throughput concerns, however,
careful consideration is needed to establish a base-line sampling, and higher levels of sampling can be considered on an
exception-basis based on automated trigger mechanisms. The goal is improved scanner control and lithographic cost of
ownership. This study addresses tools for establishing baseline sampling as well as motivation and initial results for
dynamic sampling for application to higher order modeling.
As the semiconductor industry continues to drive towards high volume production at the 50nm technology node and
beyond, there are formidable barriers imposed not only from technical challenges but also from economic challenges
related to controlling overlay tightly enough to meet the strict requirements of a increasingly smaller overlay control
window. In this paper, the authors will show potential sources overlay error for a 50nm node process and detail a
methodology to pinpoint the root cause and an application to help reduce these errors to facilitate the ramp of a new
process technology for high volume DRAM/FLASH manufacturing. In short, based on a series of experiments and
analysis, the authors have identified high-order wafer-level residual component to be the main contribution of the high
residuals with the source attributed to the scanner mix-and-match set. In turn, an overlay control approach using high
order correctables generated from the overlay metrology system and fed through the APC system will be able to
effectively reduce the mix-and-match high residual errors.
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