In this paper, an integrated optical receiver module with demultiplexer chip-to-chip optical interconnects is proposed. The receiver and demultiplexer (demux) were realized on a single chip in a 0.18 μm TSMC CMOS technology. The topology uses a 1:2 for the demux while the receiver (Rx) module consists of transimpedance amplifier (TIA) and a limiting amplifier (LA). The receiver achieved a gain of 90 dBΩ and a 3-dB bandwidth of 4.5 GHz. Clear eye diagrams were observed with a voltage swing of 375 mVpp up to 2.5 Gbps output from the Rx-Demux at 5 Gbps input signal. The integrated chip occupies an area of 594x1089 μm2 with power consumptions of 122 mA under a 1.8 V power supply This solution could be applied to CPU/memory interface where bidirectional signaling is required.
The design of a biwavelength transceiver (TRx) module for parallel simultaneous bidirectional optical interconnects is described. The TRx module has been implemented using two different wavelengths, 850 and 1060 nm, to send and receive signals simultaneously through a common optical interface while optimizing cost and performance. Filtering mirrors are formed in the optical fibers which are embedded on a V-grooved silicon substrate for reflecting and filtering optical signals from/to vertical-cavity surface-emitting laser (VCSEL)/photodiode (PD). The VCSEL and PD are flip-chip bonded on individual silicon optical benches, which are attached on the silicon substrate for optical signal coupling from the VCSEL to fiber and from fiber to the PD. A high-speed and low-loss ceramic printed circuit board, which has a compact size of 0.033 cc, has been designed to carry transmitter and receiver chips for easy packaging of the TRx module. Applied for quad small form-factor pluggable applications at 40-Gbps operation, the four-channel biwavelength TRx module showed clear eye diagrams with a bit error rate (BER) of 10 −12 at input powers of −5 and −5.8 dBm for 1060 and 850 nm operation modes, respectively.
An analytical model based on interconnect parameters is presented for the analysis of thermal effects on crosstalk and performance of multi-channel optoelectronic modules. The model is accurate for computing crosstalk of interconnects used in chip packaging. In addition, model is used to determine the thermal critical frequency, fcrit, above which signals becomes severely deteriorated and can be applied in the design and packaging of optoelectronic transmitter modules for reliable data transmission.
In this paper, a crosstalk expression and equivalent circuit model have been proposed based on RLC line model and interconnect parameters for wire-bonded and flip-chip bonded multichannel optoelectronic modules. The analytical expression and model are accurate for computing crosstalk of interconnects used in chip packaging. In addition, full-wave simulation and experimental results from total crosstalk measurement are discussed.
A simultaneous bidirectional CMOS transceiver for full duplex chip-to-chip optical interconnects is proposed, utilizing a
resistor-transconductor (R-gm) hybrid. The hybrid separates the inbound signal from the input/output compound signal.
The simultaneous bidirectional CMOS transceiver is designed in a 0.18 μm Si-CMOS technology, with power
dissipation of 79 mW and 54.4 mW for the transmitter and receiver, respectively. It shows a 3-dB bandwidth of 4.6 GHz
for both the transmitter and the receiver with a 3-dB gain of 26.6 dB and 10.6 dB, respectively, in full-duplex mode.
We propose a new dynamic D-latch for low-power high-speed SerDes in chip-to-chip optical interconnect. The overall
SerDes circuit uses 3.6 times less number of transistors, with smaller SerDes occupying 50% less area, compared to the
previous works. The SerDes operates up to 10 Gbps data rate, and the power consumption is 49.3 mW at 1.8 V, which is
30 % less power.
KEYWORDS: Clocks, Digital electronics, Eye, Analog electronics, Transistors, Field programmable gate arrays, Field effect transistors, Optical design, Switching, Multiplexing
An analog-type high-speed serializer/deserializer (SerDes) has been designed for optical links especially between CPU
and memory. The circuit uses a system clock and its phases to multiplex data to the serial link which avoids the need for
a PLL-based high frequency clock generation used in serializing parallel data as in conventional SerDes design. The
multiplexed link combined with the de-serializing clock is used as a reference signal for de-serialization. The SerDes is
being designed in a 0.13 μm Si-CMOS technology. The fabricated serializer has a core chip size of 360 x750 μm2. Power
dissipation for the SerDes is 71.4 mW operating up to 6.5 Gbps.
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