Dr. Jan-Willem Gemmink Profile

Dr. Jan-Willem Gemmink

Project Leader at ASML Netherlands BV

SPIE Involvement:

Author

Proceedings Article | 28 March 2017 Paper

Robust 2D patterns process variability assessment using CD-SEM contour extraction offline metrology

Amine Lakcher, Bertrand Le-Gratiet, Julien Ducoté, Pierre Fanton, Ton Kiers, Jan-Willem Gemmink, Stefan Hunsche, Christopher Prentice, Maxime Besacier

Proc. SPIE. 10145, Metrology, Inspection, and Process Control for Microlithography XXXI

KEYWORDS: Lithography, Metrology, Etching, Metals, Image processing, Copper, Manufacturing, Inspection, Scanning electron microscopy, Process control, Optical alignment, Semiconducting wafers, Process engineering, Chemical mechanical planarization

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Proceedings Article | 16 March 2016 Paper

Verification and application of multi-source focus quantification

J.-G. Simiz, T. Hasan, F. Staals, B. Le-Gratiet, W. Tel, C. Prentice, J.-W. Gemmink, A. Tishchenko, Y. Jourlin

Proc. SPIE. 9781, Design-Process-Technology Co-optimization for Manufacturability X

KEYWORDS: Reticles, Optical lithography, Data modeling, Visualization, Sensors, Scanners, Manufacturing, Image resolution, Time metrology, Photomasks, Semiconducting wafers, Product engineering, Performance modeling, Chemical mechanical planarization, Design for manufacturability

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Proceedings Article | 23 March 2011 Paper

Characterization and control of dynamic lens heating effects under high volume manufacturing conditions

J. Bekaert, L. Van Look, G. Vandenberghe, P. van Adrichem, M. Maslow, J.-W. Gemmink, H. Cao, S. Hunsche, J. T. Neumann, A. Wolf

Proc. SPIE. 7973, Optical Microlithography XXIV

KEYWORDS: Diffraction, Monochromatic aberrations, Reticles, Calibration, Scanners, Manufacturing, Wavefronts, Photomasks, Semiconducting wafers, HVAC controls

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Proceedings Article | 23 March 2011 Paper

Optical proximity stability control of ArF immersion clusters

Lieve Van Look, Joost Bekaert, Koen D'havé, Bart Laenens, Geert Vandenberghe, Shaunee Cheng, Koen Schreel, Jan-Willem Gemmink

Proc. SPIE. 7973, Optical Microlithography XXIV

KEYWORDS: Wafer-level optics, Diffractive optical elements, Scanners, Control systems, Scanning electron microscopy, Scatterometry, Photomasks, Critical dimension metrology, Semiconducting wafers, Fiber optic illuminators

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Proceedings Article | 19 March 2008 Paper

Yield aware design of gate layer for 45 nm CMOS-ASIC using a high-NA dry KrF systems

Ewoud Vreugdenhil, Harold Benten, Liesbeth Reijnen, Gerald Dicker, Jan-Willem Gemmink, Frank Bornebroek

Proc. SPIE. 6925, Design for Manufacturability through Design-Process Integration II

KEYWORDS: Lithography, Optical lithography, Curium, Scanners, Printing, Photomasks, Transistors, Field effect transistors, Nanoimprint lithography, Semiconducting wafers

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Proceedings Article | 2 April 2007 Paper

Early look into device level imaging with beyond water immersion

Will Conley, Scott Warrick, Cesar Garza, Pierre-Jerome Goirand, Jan-Willem Gemmink, David Van Steenwinckel

Proc. SPIE. 6520, Optical Microlithography XX

KEYWORDS: Semiconductors, Lithography, Refractive index, Polarization, Water, Manufacturing, Imaging devices, Photoresist materials, Photomasks, Photoresist developing

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Proceedings Article | 27 March 2007 Paper

Extending immersion lithography to the 32-nm node

Scott Warrick, Will Conley, Vincent Farys, Michael Benndorf, Jan-Willem Gemmink, Yorick Trouiller, Jerome Belledent, Dejan Jovanovic, Pascal Gouraud

Proc. SPIE. 6520, Optical Microlithography XX

KEYWORDS: Semiconductors, Optical lithography, Etching, Scanners, Manufacturing, Photomasks, Immersion lithography, Optical proximity correction, Photoresist processing, Semiconducting wafers

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Proceedings Article | 27 March 2007 Paper

Integrating immersion lithography in 45-nm logic manufacturing

Michael Benndorf, Scott Warrick, Will Conley, David Cruau, Danilo DeSimone, Karim Mestadi, Vincent Farys, Jan-Willem Gemmink

Proc. SPIE. 6520, Optical Microlithography XX

KEYWORDS: Semiconductors, Lithography, Logic, Scanners, Manufacturing, Immersion lithography, Source mask optimization, Critical dimension metrology, Semiconducting wafers, Overlay metrology

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Proceedings Article | 15 March 2006 Paper

Immersion lithography robustness for the C065 node

Scott Warrick, Rob Morton, Andrea Mauri, Jean-Damien Chapon, Jerome Belledent, Will Conley, Alex Barr, Kevin Lucas, Cedric Monget, Valerie Plantier, David Cruau, Juan-Manuel Gomez, Emmanuel Sicurani, Jan-Willem Gemmink

Proc. SPIE. 6154, Optical Microlithography XIX

KEYWORDS: Lithography, Optical lithography, Etching, Metals, Scanners, Manufacturing, Line width roughness, Immersion lithography, Optical proximity correction, Semiconducting wafers

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Semiconductor manufacturers are in the midst of the next technology node C045 (65nm half-pitch) development. The difference this time is that the heavy lifting is being done while swimming. Generally, for the C065 node (hp90), critical layers will be processed using 193-nm scanners with numerical apertures up to 0.85. It is also clear that the capabilities and potential benefits of immersion lithography (at this wavelength and NA) should to be examined, in addition to the development of immersion lithography for the C045 and C032 technology generations. The potential benefits of immersion lithography; increased DOF in the near term and hyper-NA imaging in the next phase, have been widely reported. A strategy of replacing conventional "dry" lithographic process steps with immersion lithographic process steps would allow the benefits of immersion to be realized much earlier. To fully realize this advantage a direct comparison of immersion lithography's benefits and therefore speed learning is needed. However, such an insertion should be "transparent": i.e. the "immersion process" should run with the same reticles (OPC) and resists, as the conventional process. In an effort to gain this knowledge about the immersion processes, we have chosen a path of optimizing and ramping-up the lithographic process for the C065 technology node. In this paper, we report on the compatibility of inserting immersion lithography processes into an established C065 process running in a pilot manufacturing line. We will present an initial assessment of some critical parameters for the implementation of immersion lithography. This assessment includes: OPC compatibility, imaging, process integration, and defectivity all compared to the dry process of record. Finally, conclusions will be made as to the overall readiness of immersion to support C065 node processing in direct transfer from dry and its extendibility to C045. In this work, the C045 technology node (hp65) is the main target vehicle. However, a successful introduction of immersion technology may allow a strategy change complementary with the previous (C065) technology node (i.e. run C065 immersion in production and benefit from larger process windows).

Proceedings Article | 14 March 2006 Paper

Design and use of multivariate approach error analysis APC system

Jean de Caunes, Joost van Herk, Scott Warrick, Bertrand Le Gratiet, Marc Mikolajczak, Jean-Damien Chapon, Cedric Monget, Jan-Willem Gemmink

Proc. SPIE. 6155, Data Analysis and Modeling for Process Control III

KEYWORDS: Semiconductors, Oxides, Reticles, Metrology, Scanners, Error analysis, Critical dimension metrology, Semiconducting wafers, Overlay metrology, Process modeling

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Showing 5 of 10 publications

Conference Committee Involvement (1)

Optical Microlithography XX

27 February 2007 | San Jose, California, United States

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