Markus Greul, Astrit Shoshi, Jan Klikovits, Stephan Martens, Ulrich Hofmann, Olga Barahona, Benyamin Shnirman, Leon Starz, Patrick Wintrich, Holger Sailer
A critical factor in the fabrication of complex nano- and microstructures with high quality and reproducibility is the determination of a suitable working point. This applies particularly to lithography, which is the basis for transferring the desired patterns onto the substrate. For this reason, we present a generic process optimization methodology that has been successfully applied to four chemically amplified positive and negative tone electron beam lithography photoresists with different sensitivities. The method is iterative and designed for the best possible results with a minimum use of resources. This is accomplished by identifying the critical key factors in photoresist processing using contrast curves and determining their impact. Starting with the most influential bake parameter, the maximum effect is achieved. The method used is similar to the Bossung plot procedure and aims for a maximum process window. After the bake parameters, the fundamentals of development kinetics are discussed, and a method for determining an appropriate development time is presented. A mask making approach is then used to investigate the ideal exposure conditions. This includes the determination of an appropriate base dose in conjunction with proximity effect correction and sizing. The evaluation of this method is demonstrated by critical dimension linearity plots and scanning electron microscope cross sectional analysis of resist profiles. The results presented demonstrate the universality of the optimization approach.
KEYWORDS: Electrons, Copper, Scattering, Monte Carlo methods, Polymethylmethacrylate, Particles, Particle contamination, Photomasks, Electron beam lithography
In this paper, we show the characteristics of particle contamination induced defect footprints and explain the basic principles of their formation during ebeam exposure. To verify these principles, we carried out full 3D Monte Carlo Simulations of electrons impinging on the mask stack (modelled as PMMA, Cr, and SiO2), covered by a defect layer and compared the simulated contour with SEM images of real defect footprints. The relevant physical property is the deposited energy inside the PMMA layer. First, we verified in our simulations that the deposited energy is indeed antiproportional to the beam energy. In a second step we simulated scattering trajectories of electrons to quantify the nontrivial dependence of deposited energy on the size and thickness of defects as well as defect composition. We also considered shotnoise statistics due to the limited number of electrons in ebeam pattern generation accompanied by gaussian smoothing of the deposited energy representing subsequent processing and demonstrate that considerably increased energy deposition to an ebeam-active resist can occur in direct vicinity of a scattering defect when scattering widens the beam opening angle leading to longer trajectories inside the resist. The pattern generator is variable-shaped electron beam (VSB) with 50 keV energy operated in the high-volume photomask manufacturing facility at AMTC Dresden, the Monte Carlo simulation software is virtualSEM from GenISys GmbH.
Mask Process Correction (MPC) is well established as a necessary step in mask data preparation (MDP) for electron beam mask manufacturing at advanced technology nodes from 14nm and beyond. MPC typically uses an electron scatter model to represent e-beam exposure and a process model to represent develop and etch process effects [1]. The models are used to iteratively simulate the position of layout feature edges and move edge segments to maximize the edge position accuracy of the completed mask. Selective dose assignment can be used in conjunction with edge movement to simultaneously maximize process window and edge position accuracy [2]. MPC methodology for model calibration and layout correction has been developed and optimized for the vector shaped beam (VSB) mask writers that represent the dominant mask lithography technology in use today for advanced mask manufacturing [3]. Multi-beam mask writers (MBMW) have recently been introduced and are now beginning to be used in volume photomask production [4]. These new tools are based on massively parallel raster scan architectures that significantly reduce the dependence of write time on layout complexity and are expected to augment and eventually replace VSB technology for advanced node masks as layout complexity continues to grow [5][6]. While it is expected that existing MPC methods developed for VSB lithography can be easily adapted to MBMW, a rigorous examination of mask error correction for MBMW is necessary to fully confirm applicability of current tools and methods, and to identify any modifications that may be required to achieve the desired CD performance of MBMW. In this paper we will present the results of such a study and confirm the readiness of MPC for multi-beam mask lithography.
As optical lithography is extended into 10nm and below nodes, advanced designs are becoming a key challenge for mask manufacturers. Techniques including advanced Optical Proximity Correction (OPC) and Inverse Lithography Technology (ILT) result in structures that pose a range of issues across the mask manufacturing process. Among the new challenges are continued shrinking Sub-Resolution Assist Features (SRAFs), curvilinear SRAFs, and other complex mask geometries that are counter-intuitive relative to the desired wafer pattern. Considerable capability improvements over current mask making methods are necessary to meet the new requirements particularly regarding minimum feature resolution and pattern fidelity. Advanced processes using the IMS Multi-beam Mask Writer (MBMW) are feasible solutions to these coming challenges. In this paper, we study one such process, characterizing mask manufacturing capability of 10nm and below structures with particular focus on minimum resolution and pattern fidelity.
As optical lithography is extended into 10nm and below nodes, advanced designs are becoming a key challenge for mask
manufacturers. Techniques including advanced optical proximity correction (OPC) and Inverse Lithography
Technology (ILT) result in structures that pose a range of issues across the mask manufacturing process. Among the
new challenges are continued shrinking sub-resolution assist features (SRAFs), curvilinear SRAFs, and other complex
mask geometries that are counter-intuitive relative to the desired wafer pattern. Considerable capability improvements
over current mask making methods are necessary to meet the new requirements particularly regarding minimum feature
resolution and pattern fidelity. Advanced processes using the IMS Multi-beam Mask Writer (MBMW) are feasible
solutions to these coming challenges. In this paper, Part 2 of our study, we further characterize an MBMW process for
10nm and below logic node mask manufacturing including advanced pattern analysis and write time demonstration.
Reticles for manufacturing upcoming 10nm and 7nm Logic devices will become very complex, no matter whether 193nm water immersion lithography will continue as main stream production path or EUV lithography will be able to take over volume production of critical layers for the 7nm node. The economic manufacturing of future masks for 193i, EUV and imprint lithography with further increasing complexity drives the need for multi-beam mask writing as this technology can overcome the influence of complexity on write time of today’s common variable shape beam writers. Local registration of the multi-beam array is a critical component which greatly differs from variable shape beam systems. In this paper we would like to present the local registration performance of the IMS Multi-Beam Mask Writer system and the metrology tools that enable the characterization optimization.
Since multi electron beam exposure has become a serious contender for next generation mask making, proximity- and
process effect corrections (PEC) need to be adapted to this technology. With feature sizes in the order of the short-range
blurs (resist and tool), contrast enhancements need to be combined with standard linearity corrections. Different PEC
strategies are reviewed and compared with respect to their suitability for multi-beam exposure. This analysis
recommends a hybrid approach that combines the benefits of shape- and dose PEC and is optimally applicable for multibeam
exposure. Exposure results on the proof-of-concept 50keV electron multi-beam mask exposure tool (eMET POC) and a standard
50 kV vector shaped beam tool (VSB) are shown to verify that the combined PEC with overdose contrast enhancement
covers the whole pattern range from isolated to opaque.
Electron multi-beam mask writers address the challenge of long mask write times for increasingly complex masks. The writing speed of the IMS multi-beam mask writer under consideration here depends on the data path and blanking device speed provided for exposing the patterns. It was initially believed that the maximum dose required for exposing the patterns could also be a limiting factor. We present a proximity effect correction scheme that improves image quality (compared to a dose-only correction) and allows for a maximum dose limit. We test this scheme with and without maximum dose limit, and compare the achieved image quality against that for a dose-only correction. The results of this simulation study are verified by comparing top down SEM images of resist structures from exposures using the different corrections.
Using electron beam direct write (EBDW) as a complementary approach together with standard optical lithography at
193nm or EUV wavelength has been proposed only lately and might be a reasonable solution for low volume CMOS
manufacturing and special applications as well as design rule restrictions. Here, the high throughput of the optical litho
can be combined with the high resolution and the high flexibility of the e-beam by using a mix & match approach (Litho-
Etch-Litho-Etch, LELE). Complementary Lithography is mainly driven by special design requirements for unidirectional
(1-D gridded) Manhattan type design layouts that enable scaling of advanced logic chips. This requires significant data
prep efforts such as layout splitting.
In this paper we will show recent results of Complementary Lithography using 193nm immersion generated 50nm
lines/space pattern addressing the 32nm logic technology node that were cut with electron beam direct write. Regular
lines and space arrays were patterned at GLOBALFOUNDRIES Dresden and have been cut in predefined areas using a
VISTEC SB3050DW e-beam direct writer (50KV Variable Shaped Beam) at Fraunhofer Center Nanoelectronic
Technologies (CNT), Dresden, as well as on the PML2 tool at IMS Nanofabrication, Vienna. Two types of e-beam
resists were used for the cut exposure. Integration issues as well as overlay requirements and performance improvements
necessary for this mix & match approach will be discussed.
Basic concept and targeted throughput values for IMS Nanofabrication's 50keV electron multibeam Mask Exposure
Tool called eMET are outlined and detailed specifications of an eMET Proof-of-Concept Tool are presented. Recent
results as obtained with electron and ion multi-beam projection test systems are described and compared with exposure
simulations. Exposures were concentrated on ILT as well as OPC test patterns. Good agreement between test system
exposures and simulation results is shown proving the accuracy of the theoretical predictions. Aerial image simulations
for eMET demonstrate its capability to fully resolve complex patterns down to the 8 nm mask technology node.
Multi-beam writing becomes mandatory for future technology nodes in order to stay within reasonable realization times
for leading-edge complex masks and templates. IMS Nanofabrication has developed multi-beam projection techniques
implementing a programmable aperture plate system (APS) and charged-particle projection optics with 200x reduction.
Proof-of-concept of multi-beam writing on static substrates was demonstrated in 2009 using the CHARPAN tool with
10keV ion multi-beams and the RIMANA tool with 50keV electron multi-beams. For the first time projection multibeam
writing on moving substrates is presented as made achievable by upgrading the CHARPAN Tool with a laserinterferometer
controlled stage to realize a POWS (Proof-Of-Writing-Strategy) tool configuration. With the RIMANA
Tool 50keV e-beam exposures of ILT (Inverse Lithography Technique) patterns are demonstrated.. The status of the
development of a 50keV electron Mask Exposure Tool (eMET) is presented and the targeted writing speeds of eMET
POC and eMET HVM systems are outlined.
Projection Mask-Less Lithography (PML2) is a potentially
cost-effective electron multi-beam solution for the 16 nm hp
ITRS technology node and beyond. First results obtained with a PML2 Testbench are presented where a programmable
Aperture Plate System (APS) was used to generate ca. 2500
micrometer-sized beams which are projected onto wafer
level with 200x demagnification. The APS contains CMOS electronics which allows for addressable deflection of
selected beams; only non-deflected beams make it to the wafer surface to achieve 12.5 nm spot size. Beam energy
(50keV) and current density (~2 A/cm2) are the same as in future PML2 production tools. Thus, the results obtained with
the PML2 Testbench unambiguously prove the patterning capabilities of the PML2 technology.
KEYWORDS: Semiconducting wafers, Lithography, Electron beams, Electrodes, Prototyping, Electron beam lithography, Electron beam direct write lithography, Silicon, Optical alignment, Photomasks
Projection Mask-Less Lithography (PML2) is a potentially cost-effective multi electron-beam
solution for the 22 nm half-pitch node and beyond. PML2 is targeted on using hundreds of
thousands of individually addressable electron-beams working in parallel, thereby pushing
the potential throughput into the wafers per hour regime. With resolution potential of < 10
nm, PML2 is designed to meet the requirements of several upcoming tool generations.
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