Mr. Jean-Marc Thevenoud Profile

Jean-Marc Thevenoud

at Alcatel Vacuum Technology

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Proceedings Article | 27 December 2006 Paper

High-productivity DRIE solutions for 3D-SiP and MEMS volume manufacturing

M. Puech, J. Thevenoud, N. Launay, N. Arnal, P. Godinat, B. Andrieu, J. Gruffat

Proceedings Volume 6415, 64150I (2006) https://doi.org/10.1117/12.695242

KEYWORDS: Etching, Semiconducting wafers, Deep reactive ion etching, Silicon, Plasma, Microelectromechanical systems, Polymers, Manufacturing, Control systems design, Imaging systems

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Emerging 3D-SiP technologies and high volume MEMS applications require high productivity mass production DRIE systems. The Alcatel DRIE product range has recently been optimized to reach the highest process and hardware production performances. A study based on sub-micron high aspect ratio structures encountered in the most stringent 3D-SiP has been carried out. The optimization of the Bosch process parameters have shown ultra high silicon etch rate, with unrivaled uniformity and repeatability leading to excellent process yields. In parallel, most recent hardware and proprietary design optimization including vacuum pumping lines, process chamber, wafer chucks, pressure control system, gas delivery are discussed. A key factor for achieving the highest performances was the recognized expertise of Alcatel vacuum and plasma science technologies. These improvements have been monitored in a mass production environment for a mobile phone application. Field data analysis shows a significant reduction of cost of ownership thanks to increased throughput and much lower running costs. These benefits are now available for all 3D-SiP and high volume MEMS applications. The typical etched patterns include tapered trenches for CMOS imagers, through silicon via holes for die stacking, well controlled profile angle for 3D high precision inertial sensors, and large exposed area features for inkjet printer head and Silicon microphones.

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