The on-product overlay specification and Advanced Process Control (APC) are getting extremely challenging
particularly after the introduction of multi-patterning applications like Litho-Etch-Litho-Etch (LELE). While the Reticle
Writing Error (RWE) contribution could be marginalized for quite some time in the layer-to-layer overlay budget, it will
become one of the dominating overlay contributors when the intra-layer overlay budget is considered. While most of the
overlay contributors like wafer processing, scanner status, reticle transmission, dose, illumination conditions drop out of
the intra-layer overlay budget, this is certainly not the case for reticle to reticle writing differences.
In this work, we have studied the impact of the RWE on the on-product overlay performance. We show that the RWE
can be characterized by an off-line mask registration tool and the modelled results can be sent as feed-forward
corrections to the ASML TWINSCANTM. By doing so, the overlay control complexity (e.g. send-ahead wafers, APC
settling time) can be reduced significantly. Off-line characterization enables that all reticles virtually become equal after
correction (at least to the level of correction capability of the scanner). This means that all higher order RWE
contributions (currently up to a third order polynomial) can be removed from the fingerprint. We show that out of 50
production reticles (FEOL, 28-nm technology), 30% can be improved on residual level when non-linear feed-forward
corrections are considered as well. The additional benefit of feeding forward linear corrections to the scanner is even
higher: it is anticipated that a large portion of the APC variation might find its origin in the RWE contribution.
In order to send feed-forward corrections to the scanner, we obviously rely on the quality of the off-line RWE
measurements. These measurements are usually provided by a registration tool at the mask shop. To secure the quality,
an independent experimental verification test was developed to check if off-line RWE measurements can be used as
feed-forward corrections to the scanner. The test has been executed on an ASML NXT: 1950i scanner and was designed
such to isolate the reticle writing error contribution. The match between the off-line measurements and the experiment is
High volume semiconductor manufacturing yields require that critical resist feature profile is continually controlled for
uniformity and centering. One reason is the small working distance of high numerical aperture lenses. Indeed, reducing
process windows require more precise dimensional control. The variation of the critical dimensions can generally be
attributed to the lack of the focus and/or dose control. A methodology to control the two lithographic parameters and to
construct a focus and dose budget for all components (tool, layer, resist, and reticle) has been developed. This paper
presents a run-to-run control called FDO1 (Focus Dose Optimization) using in-line CD metrology. We have confirmed
that this method controls the photoresist shape and the photoresist width accurately and reduces the CD variation for 28
nm devices by 50%.
The main difficulty related to DoseMapper correction is to generate an appropriate CD datacollection to feed
DoseMapper and to generate DoseRecipe in a user friendly way, especially with a complex process mix.
We could heavily measure the silicon and create, in feedback mode, the corresponding DoseRecipe. However, such
approach in a logic fab becomes a heavy duty due to the number of different masks / product / processes. We have
observed that process CD variability is significantly depending on systematic intrawafer and intrafield CD footprints that
can be measured and applied has generic pre-correction for any new product/mask process in-line. The applied CD
correction is based on a CD (intrafield: Mask + Straylight & intrawafer: Etch Bias) variability "model" handled by the
FAB APC (Advanced Process Control).
- Individual CD profile correction component are generated "off-line" (1) for Intrafield Mask via
automatic CD extraction from a Reticle CD database (2) for Intrafield Straylight via a CD "model" (3)
for Intrawafer Etch Bias via engineering input based on process monitoring.
- These CD files are handled via the FAB APC/automation system which is remotely taking control of
DoseMapper server via WEB services, so that CD profiles are generated "off-line" (before the lot is
being processed) and stored in a profile database while DoseRecipes are created "real-time" on
demand via the automation when the lot comes to the scanner to be processed. DoseRecipe and CD
correction profiles management is done via the APC system.
The automated DoseRecipe creation is now running since the beginning of 2011 contributing to bring both intrafield and
intrawafer GATE CDu below 1nm 3sigma, for 45/40 & 28nm nodes.
As design rules continue to shrink, it is increasingly important to be able to determine and separate sources of Critical
Dimension (CD) errors in order to maintain ever-decreasing process windows. CD errors can mainly be attributed to lack
of focus and dose control1. Today some of these errors go undetected and CD changes are corrected by making dose
correction to the exposure tool. However, corrections using only dose can lead to significantly smaller process latitudes.
Therefore, it is very important that we consider dose and focus as a pair to increase the CD uniformity. The model we use
is based on Ausschnitt deconvolution method1, 2. This model calculates the dose and focus errors simultaneously from
CD parameters, such as bottom CD and top CD information, measured by a scatterometry measurement tool. We have
confirmed that this method controls photoresist shape and photoresist width accurately and reduces the CD variation for
40 nm devices by 50%.
Since 2008, we have been presenting some papers regarding CMOS 45nm logic gate patterning activity to
reduce CD dispersion. After a global CD budget evaluation at SPIE08, we have been focusing on Intrafield CD
corrections using Dose MapperTM. The story continues and since then we have pursued our intrafield characterisation
and focus on ways to get Dose MapperTM dose recipe created before the first silicon is coming. In fact 40nm technology
is already more demanding and we must be ready with integrated solutions for 32/28nm node.
Global CD budget can be divided in Lot to Lot, Wafer to Wafer, Intra wafer and Intra field component. We
won't talk here about run to run solutions which are put in place for Lot to Lot and Wafer to Wafer. We will emphasize
on the intrafield / intrawafer process corrections and outline process compensation control and strategy. A lot of papers
regarding intrafield CD compensation are available in the litterature but they do not necesserally fit logic manufacturing
needs or possibilities. We need to put similar solutions in place which are comprehensive and flexible. How can we
correct upfront an Etch chamber CD profile combined with a mask and scanner CD signature? How can we get intrafield
map from random logic devices? This is what we will develop in this paper.
CMOS 45nm technology, and especially the logic gate patterning has led us to hunt for every nanometer we
could found to reach aggressive targets in term of overall CD budget. We have presented last year a paper ("Process
Control for 45 nm CMOS logic gate patterning " - B. Le Gratiet SPIE2008; 6922-33) showing the evaluation of our
process at that time. One of the key item was the intrafield control. Preliminary data were presented regarding intrafield
CD corrections using Dose MapperTM. Since then, more work has been done in this direction and not only for the GATE
Depending on reticle specification grade, process MEEF and scanner performance, intrafield CD variation can
reach quite high CD ranges and become a non negligeable part of the overall budget. Although reticles can achieve very
good level of CD uniformity, they all have their own "footprint" which will becomes a systematic error. The key point
then is to be able to measure this footprint and correct for it on the wafer. Scanners suppliers provide tools like Dose
MapperTM to modify the intrafield exposure dose profile. Generating and using a proper exposure "subrecipe" requires
intrafield in-line control needs on production wafers. This paper present a status of our work on this subject with some
results related to global gate CMOS 45nm CD variability improvement including etch process compensation with Dose
Nanoimprint Lithography appears to be a competitive candidate for Next Generation Lithography in semiconductor
industry due to its advantages concerning resolution and cost effectiveness. Moreover, UV-Nanoimprint Lithography
(UV-NIL) should enable to reach good overlay values, which is also a major criterion for integration.
In this paper, we present first integration results which were obtained on lines and contact holes. A specific template was
designed for this purpose in collaboration with CEA-LETI, IMS and Molecular Imprints. This template was
characterized by using various techniques (optical and SEM techniques) and showed quite a good quality of the
template; in particular, 50 nm holes were defined.
Molecular Imprints process was then tested by using Imprio55® at MESA+ Research Institute, University of Twente
(Netherlands). In these experiments, 37 4.8 cm2 fields were imprinted on Double Side Polished wafers. For each field, 52
droplets were dispensed with various volumes. Resolution and non-uniformity were evaluated after imprinting. Then
etching tests were performed.
This paper present an evaluation of our CMOS 45nm gate patterning process performance based on immersion
lithography in a production environment. A CD budget breakdown is shown detailing lot to lot, wafer to wafer,
intrawafer, intrafield and proximity CD uniformity characterization. Emphasis is given on scatterometry library
development and deployment. We also look more into detail to focus effect on CD control. Finally status of overlay
performance with immersion lithography is also presented.
In this paper we performed an analysis of various data collection preformed on C045 production lots in order to
assess the influence of STI oxide layers on the CD uniformity of implant photolithography layers. Our final purpose is to
show whether the DOSE MAPPERTM software option for interfiled dose correction available on ASML scanners
combined with a run-to-run feed-forward regulation loop could improve global CD uniformity on C045 implants layers.
After a brief presentation of the C045 implants context the results of the analysis are presented : swing curves, process
windows analysis, and intra-die CD measurements are presented. The conclusion of the analysis is that it is not possible,
in the current C045 industrial environment, to use a robust and general method of interfield dose correction in order to
achieve a better global CD uniformity.