Since the beginning of the Crolles 300mm fab, more and more complex logic technologies, down to 28nm node, have been developed. At the same time, the products mix increased at a very high level : Specifically for the lithography area, this complexity leads to an intricate management of thousands of masks, hundreds of track process recipes, used on various lithography clusters types (193nm including immersion, 248nm and 365nm). In order to apply the best process parameters, APC software is used since many years, and was continuously improved. It now takes into account multi-variate parameters coming from various process contexts. A new sampling tool was developed to adjust the measurements control plan. All kind of in-line measures are addressed (thickness, critical dimensions, overlay…). Since the beginning of this software development, the approach was to keep in mind the APC model. The objective was to use the APC data’s (alarms and warnings) to secure the sampling decisions without compromising the regulation loops stability.
This sampling tool can use different inputs (production, tools, APC…) in a dynamic way. This means that the system is dynamic for both process and metrology aspects, and can be adapted to integrate different variables and external events. A real time communication flow was created between APC and sampling tool. Even if the measurement skip decision is taken by the sampling tool, the APC feedback is systematically requested when run to run is involved, like for all lithography process steps. The strength is to deal with high products / mix complexity and react in real time to new product introduction, process deviation, atypical lots including R&D projects and sudden change of the products mix. Both tools are so linked that the sampler remains invisible. Process engineers continue to manage and control lithography process through APC tool mainly.
In parallel, different alarms and triggers have been implemented, including a specific “crisis” mode to quickly respond to the metrology equipment loading or availability variability.
The sampler introduction allowed an optimization of the metrology toolset costs and lot cycle time improvement. Also as a consequence, a more efficient metrology control plan, with an optimized balance between process criticality and metrology requirements.
Future opportunities are related to more dynamic behaviors, as a dynamic sampling rate adapted to metrology capacity, function of the real time metrology capacity or sampling decision dynamically based on process variability components.
Derivative technology like embedded Non-Volatile Memories (eNVM) is raising new types of challenges on the “more than Moore” path. By its construction: overlay is critical across multiple layers, by its running mode: usage of high voltage are stressing leakages and breakdown, and finally with its targeted market: Automotive, Industry automation, secure transactions… which are all requesting high device reliability (typically below 1ppm level). As a consequence, overlay specifications are tights, not only between one layer and its reference, but also among the critical layers sharing the same reference. This work describes a broad picture of the key points for multilayer overlay process control in the case of a 28nm FD-SOI technology and its derivative flows. First, the alignment trees of the different flow options have been optimized using a realistic process assumptions calculation for indirect overlay. Then, in the case of a complex alignment tree involving heterogeneous scanner toolset, criticality of tool matching between reference layer and critical layers of the flow has been highlighted. Improving the APC control loops of these multilayer dependencies has been studied with simulations of feed-forward as well as implementing new rework algorithm based on multi-measures. Finally, the management of these measurement steps raises some issues for inline support and using calculations or “virtual overlay” could help to gain some tool capability. A first step towards multilayer overlay process control has been taken.
For C040 technology and below, photolithographic depth of focus control and dispersion improvement is essential to secure product functionality. Critical 193nm immersion layers present initial focus process windows close to machine control capability. For previous technologies, the standard scanner sensor (Level sensor - LS) was used to map wafer topology and expose the wafer at the right Focus. Such optical embedded metrology, based on light reflection, suffers from reading issues that cannot be neglected anymore. Metrology errors are correlated to inspected product area for which material types and densities change, and so optical properties are not constant. Various optical phenomena occur across the product field during wafer inspection and have an effect on the quality and position of the reflected light. This can result in incorrect heights being recorded and exposures possibly being done out of focus. Focus inaccuracy associated to aggressive process windows on critical layers will directly impact product realization and therefore functionality and yield. ASML has introduced an air gauge sensor to complement the optical level sensor and lead to optimal topology metrology. The use of this new sensor is managed by the AGILE (Air Gauge Improved process LEveling) application. This measurement with no optical dependency will correct for optical inaccuracy of level sensor, and so improve best focus dispersion across the product. Due to the fact that stack complexity is more and more important through process steps flow, optical perturbation of standard Level sensor metrology is increasing and is becoming maximum for metallization layers. For these reasons AGILE feature implementation was first considered for contact and all metal layers. Another key point is that standard metrology will be sensitive to layer and reticle/product density. The gain of Agile will be enhanced for multiple product contribution mask and for complex System on Chip. Into ST context (High mix logic Fab) in term of product and technology portfolio AGILE corrects for up to 120nm of product topography error on process layer with less than 50nm depth of focus Based on tool functionalities delivered by ASML and on high volume manufacturing requirement, AGILE integration is a real challenge. Regarding ST requirements “Automatic AGILE” functionality developed by ASML was not a turnkey solution and a dedicated functionality was needed. A “ST homemade AGILE integration” has been fully developed and implemented within ASML and ST constraints. This paper describes this integration in our Advanced Process Control platform (APC).
Patterning process control has undergone major evolutions over the last few years. Critical dimension, focus, and overlay control require deep insight into process-variability understanding to be properly apprehended. Process setup is a complex engineering challenge. In the era of mid k1 lithography (>0.6), process windows were quite comfortable with respect to tool capabilities, therefore, some sources of variability were, if not ignored, at least considered as negligible. The low k1 patterning (<0.4) era has broken down this concept. For the most advanced nodes, engineers need to consider such a wide set of information that holistic processing is often mentioned as the way to handle the setup of the process and its variability. The main difficulty is to break down process-variability sources in detail and be aware that what could have been formerly negligible has become a very significant contributor requiring control down to a fraction of a nanometer. The scope of this article is to highlight that today, engineers have to zoom deeper into variability. Even though process tools have greatly improved their capabilities, diminishing process windows require more than tool-intrinsic optimization. Process control and variability compensations are major contributors to success. Some examples will be used to explain how complex the situation is and how interlinked processes are today.
Advanced CMOS nodes require more and more information to get the wafer process well setup. Process tool intrinsic capabilities are not sufficient to secure specifications. APC systems (Advanced Process Control) are being developed in waferfab to manage process context information to automatically adjust and tune wafer processing. The APC manages today Run to Run component from and between various process steps plus a sub-recipes/profiles corrections management. This paper will outline the architecture of an integrated/holistic process control system for a high mix advanced logic waferfoundry.
We introduced a very simple overlay feed forward correction based on lot data issued from previous lithography operations. Simple method for correction factor optimization was also proposed. We applied this method in various cases based on 28nm node early production: implants lithography on 248nm tools, contact holes double patterning on 193nm immersion tool, and we also tried to improve contact holes patterning based on 248nm lithography data. All analysis were based on early production 28nm node data mixing 28LP and 28FDSOI technologies. We first optimized the correction based on our simple approach, and then compute the dispersion of all linear overlay parameters. Maximum modeled overlay error was also computed. In most cases we obtained significant improvements. The interest of such a very simple approach that requires reduced software development and allows simple implementation was thus demonstrated.
The main difficulty related to DoseMapper correction is to generate an appropriate CD datacollection to feed
DoseMapper and to generate DoseRecipe in a user friendly way, especially with a complex process mix.
We could heavily measure the silicon and create, in feedback mode, the corresponding DoseRecipe. However, such
approach in a logic fab becomes a heavy duty due to the number of different masks / product / processes. We have
observed that process CD variability is significantly depending on systematic intrawafer and intrafield CD footprints that
can be measured and applied has generic pre-correction for any new product/mask process in-line. The applied CD
correction is based on a CD (intrafield: Mask + Straylight & intrawafer: Etch Bias) variability "model" handled by the
FAB APC (Advanced Process Control).
- Individual CD profile correction component are generated "off-line" (1) for Intrafield Mask via
automatic CD extraction from a Reticle CD database (2) for Intrafield Straylight via a CD "model" (3)
for Intrawafer Etch Bias via engineering input based on process monitoring.
- These CD files are handled via the FAB APC/automation system which is remotely taking control of
DoseMapper server via WEB services, so that CD profiles are generated "off-line" (before the lot is
being processed) and stored in a profile database while DoseRecipes are created "real-time" on
demand via the automation when the lot comes to the scanner to be processed. DoseRecipe and CD
correction profiles management is done via the APC system.
The automated DoseRecipe creation is now running since the beginning of 2011 contributing to bring both intrafield and
intrawafer GATE CDu below 1nm 3sigma, for 45/40 & 28nm nodes.
In the last years a flourishing number of techniques such as High Order Control or mappers have been proposed to improve overlay control. However a sustainable improvement requires sometimes understanding the
underlying causes of the overlay limiting factors in order to remove them when possible or at least to keep them under
control. Root cause finding for overlay error is a tough task due the very high number of influencing parameters and the
interaction of the usage conditions.
This paper presents a breakdown methodology to deal with this complexity and to find the contributors of
overlay error variation. We use a Partial Least Squares (PLS) algorithm to isolate the key contributors for correctable
terms and a field-to-field linear regression technique to highlight the main causes of residuals. We present a study
carried out on 45nm CMOS contact-gate overlay over 687 production wafers exposed in an ASML TWINSCAN XT:1700i Immersion scanner. We present the results of the correlations with the 180 process and equipment variables used for this study. For each isolated contributor we propose an explanation of the underlying physical phenomenon and solutions.
This paper present an evaluation of our CMOS 45nm gate patterning process performance based on immersion
lithography in a production environment. A CD budget breakdown is shown detailing lot to lot, wafer to wafer,
intrawafer, intrafield and proximity CD uniformity characterization. Emphasis is given on scatterometry library
development and deployment. We also look more into detail to focus effect on CD control. Finally status of overlay
performance with immersion lithography is also presented.
On-going complex integration schemes and developments in processes present significant challenges to lithography in manufacturing advanced semiconductor integrated circuits. Although APC solutions are in place to assist in achieving robust CD control and overlay, there is a great need to increase the 'knowledge' of the system with respect to other contributors impacting the process. The problem becomes more complex in case of an ASIC Prototyping Fab where there is no big runner concept. This leads to the need of a product effect management requirement (Product layout and reticles impact). For this reason, we developed the multivariate R2R controller. This paper discusses the multi-variant methodology and results of a new R2R regulation algorithm in a 65nm node process. Specifically, parameters such as linear combinations of terms, alignment variation for overlay modeled parameters (inter-field / intra-field), CD impacts (reticles, process, tool, STI stack etc) are studied. New solutions for future technology nodes are presented in this paper. It includes for each contributor a multivariate method to assess vector responses and noise contribution. This is being applied on CD and Overlay measurement feedback. For each source of variation (or "Contributor"), the multivariate controller provides the estimated level of compensation requested to meet the target and the level of noise induced on lot processing. At the moment the multivariate R2R controller runs in production. A real evaluation of the existing sources of variations and noise is possible and demonstrated. The result is a significant regulation performance improvement.