This paper discusses the further development of JPL’s n-type superlattice doping (2D doping) process for sensitivity and stability enhancement of backside illuminated (BSI), p-channel CCDs and PMOS pixel CMOS imaging arrays. We discuss the results of the n-type 2D-doping of SRI’s backside illuminated PMOS pixel 4k×4k and 8k×8k CMOS imagers. We briefly describe the backside processing parameters for the optimization of the 2D-doping process and antireflection coating design. Performance characterization, including quantum efficiency (QE), dark signal, and modulation transfer function (MTF) as a function of silicon epitaxial thickness and operating temperature will be discussed. These will be compared with the performance of devices produced using SRI’s standard BSI processes.
Access to the requested content is limited to institutions that have purchased or subscribe to SPIE eBooks.
You are receiving this notice because your organization may not have SPIE eBooks access.*
*Shibboleth/Open Athens users─please
sign in
to access your institution's subscriptions.
To obtain this item, you may purchase the complete book in print or electronic format on
SPIE.org.
INSTITUTIONAL Select your institution to access the SPIE Digital Library.
PERSONAL Sign in with your SPIE account to access your personal subscriptions or to use specific features such as save to my library, sign up for alerts, save searches, etc.