Currently, there are many developments in the field of EUV lithography that are helping to move it towards increased high volume manufacturing (HVM) feasibility. Targeted improvements in hardware design for advanced lithography are of key interest to our group, specifically metrics such as line width roughness (LWR) smoothing, dose reduction processes, and defect mitigation. In this study, we investigate how novel hardware solutions currently available on our SCREEN DT-3000 coat-develop track system, can be used as complementary non-patterning approaches to boost resist scaling even further. The utility of SCREEN non-standard hardware features to enhance overall lithography performance of a main chain scission EUV resist was deeply explored, and new process approaches were successfully identified. We hereby present our work utilizing the SCREEN DT- 3000 coat-develop track system with an ASML NXE:3400 to improve sensitivity, CD uniformity, line width roughness, and defectivity levels of aggressive dense L/S patterns.
The availability of EUV lithography is the mainstream for resolving critical dimension of the advanced technology nodes, currently in the range of 18nm and below . The first insertion of EUVL into manufacturing utilizes chemically amplified resist (CAR) . The filtration of CAR, both at bulk and point-of-use (POU), has already demonstrated in ArF and ArF immersion lithography to play a significant role for microbridges reduction essentially by removing hard particle and gels [3-6]. With respect to ArFi, EUV is bringing new challenges not only for the achievement of the required line roughness, sensitivity and resolution, but also for the need of a substantial reduction of defects such as line collapse, microbridges and broken lines. In this study, it demonstrated the ability of utilizing novel POU filtration to modulate microbridges and achieving superior start-up behavior, both crucial for enabling EUVL at high volume manufacturing. Different POU filters were tested at the imec EUV cluster comprised of TEL CleanTrack LITHIUS Pro-Z and ASML NXE:3400B. The start-up performance, assessed by measuring defects down to 19nm size as a function of the flushing solvent volume, has shown the fast achievement of attaining a stable baseline. Lithography experiments targeting reduction of on-wafer defectivity, carried out with commercially available photoresists, have consistently shown a substantial reduction of after resist development (ADI) and after resist etch (AEI) microbridges on a 16nm L/S test vehicles. The effect of membrane physical intrinsic designs and novel cleaning of POU devices are discussed.
Currently, there are many developments in the field of advanced lithography that are helping to move it towards increased HVM feasibility1,2,3,4. Targeted improvements in hardware design for advanced lithography are of interest to our group specifically for HVM metrics such as LWR improvement, dose reduction processes, and defect density reduction. In this work we are building on our experience to improve LWR in an advanced lithographic process by employing novel hardware solutions on our SCREEN DUO coat develop track system5 . Our approach is to implement post-litho annealing to improve resist line roughness. Although it is preferable to achieve such improvements post-etch process we feel, as many do, that post-patterning improvements are a precursor to improvements after etching6 . We hereby present our work utilizing the SCREEN DUO coat develop track system to improve aggressive dense L/S patterns.
Proc. SPIE. 10146, Advances in Patterning Materials and Processes XXXIV
KEYWORDS: Lithography, Particles, Scanning electron microscopy, Photoresist materials, Frequency modulation, Finite element methods, Bridges, Line width roughness, Fermium, Immersion lithography, Line edge roughness, Semiconducting wafers
Specific “killer-defects”, such as micro-line-bridges are one of the key challenges in photolithography’s advanced applications, such as multi-pattern. These defects generate from several sources and are very difficult to eliminate. Pointof-use filtration (POU) plays a crucial role on the mitigation, or elimination, of such defects. Previous studies have demonstrated how the contribution of POU filtration could not be studied independently from photoresists design and track hardware settings. Specifically, we investigated how an effective combination of optimized photoresist, filtration rate, filtration pressure, membrane and device cleaning, and single and multilayer filter membranes at optimized pore size could modulate the occurrence of such defects [1, 2, 3 and 4]. However, the ultimate desired behavior for POU filtration is the selective retention of defect precursor molecules contained in commercially available photoresist. This optimal behavior can be achieved via customized membrane functionalization. Membrane functionalization provides additional non-sieving interactions which combined with efficient size exclusion can selectively capture certain defect precursors. The goal of this study is to provide a comprehensive assessment of membrane functionalization applied on an asymmetric ultra-high molecular weight polyethylene (UPE) membrane at different pore size. Defectivity transferred in a 45 nm line 55 nm space (45L/55S) pattern, created through 193 nm immersion (193i) lithography with a positive tone chemically amplified resist (PT-CAR), has been evaluated on organic under-layer coated wafers. Lithography performance, such as critical dimensions (CD), line width roughness (LWR) and focus energy matrix (FEM) is also assessed.
Extreme ultraviolet (EUV) lithography is crucial to enabling technology scaling in pitch and critical dimension (CD). Currently, one of the key challenges of introducing EUV lithography to high volume manufacturing (HVM) is throughput, which requires high source power and high sensitivity chemically amplified photoresists. Important limiters of high sensitivity chemically amplified resists (CAR) are the effects of photon shot noise and resist blur on the number of photons received and of photoacids generated per feature, especially at the pitches required for 7 nm and 5 nm advanced technology nodes. These stochastic effects are reflected in via structures as hole-to-hole CD variation or local CD uniformity (LCDU). Here, we demonstrate a synergy of film stack deposition, EUV lithography, and plasma etch techniques to improve LCDU, which allows the use of high sensitivity resists required for the introduction of EUV HVM. Thus, to improve LCDU to a level required by 5 nm node and beyond, film stack deposition, EUV lithography, and plasma etch processes were combined and co-optimized to enhance LCDU reduction from synergies.
Test wafers were created by depositing a pattern transfer stack on a substrate representative of a 5 nm node target layer. The pattern transfer stack consisted of an atomically smooth adhesion layer and two hardmasks and was deposited using the Lam VECTOR PECVD product family. These layers were designed to mitigate hole roughness, absorb out-of-band radiation, and provide additional outlets for etch to improve LCDU and control hole CD. These wafers were then exposed through an ASML NXE3350B EUV scanner using a variety of advanced positive tone EUV CAR. They were finally etched to the target substrate using Lam Flex dielectric etch and Kiyo conductor etch systems. Metrology methodologies to assess dimensional metrics as well as chip performance and defectivity were investigated to enable repeatable patterning process development.
Illumination conditions in EUV lithography were optimized to improve normalized image log slope (NILS), which is expected to reduce shot noise related effects. It can be seen that the EUV imaging contrast improvement can further reduce post-develop LCDU from 4.1 nm to 3.9 nm and from 2.8 nm to 2.6 nm. In parallel, etch processes were developed to further reduce LCDU, to control CD, and to transfer these improvements into the final target substrate. We also demonstrate that increasing post-develop CD through dose adjustment can enhance the LCDU reduction from etch. Similar trends were also observed in different pitches down to 40 nm. The solutions demonstrated here are critical to the introduction of EUV lithography in high volume manufacturing. It can be seen that through a synergistic deposition, lithography, and etch optimization, LCDU at a 40 nm pitch can be improved to 1.6 nm (3-sigma) in a target oxide layer and to 1.4 nm (3-sigma) at the photoresist layer.