Grayscale lithography is a well-known technique for three dimensional structuring of a photo sensitive material. The 3D structuring of the photoresist is performed by a spatially variable exposure. Pixelated grayscale mask structures are defined to achieve the desired 3D resist patterns by locally variable transmittance values. Within power semiconductor processing, grayscale techniques could beneficially be applied in different process steps. Several ideas come to mind for process simplification, alternative integration scheme and more, e.g. the realization of 3D resist patterns for implant applications in order to control the doping depth and profiles and their influence on device parameters. In order to make the grayscale process useful for manufacturing of semiconductor devices it is necessary to master and consider the inherent process variability. Lithographic simulation is used to optimize the sub-resolution photo-mask features and to predict the final resist shape and its variability. Device simulation for a DMOS device, used in our 130nm technology node, shows that the device performance would benefit from an attenuation of the implant dose in the center of the device, which could be achieved by creating a resist island with reduced resist thickness in the center of the drawn implant opening of the DMOS device. In order to achieve the desired target geometry of the implant resist mask, simulations with Sentaurus Lithography have been performed resulting in a suitable mask design and lithographic process. We will demonstrate the development of the grayscale litho-process based on the needs of an implant scheme that is going to be used for a DMOS device, with respect to process stability and achieved resist mask dimensions.
The use of TiN-Hard masks for Cu metal layer patterning has become a common technique for trench first metal hard mask (TFMH) back end of line (BEOL) integration schemas. Resist rework influences the chemical and physical behavior of the TiN hard mask and therefore the final result of the dual damascene etch process in terms of critical line dimension (CD) and trench taper determining the electrical metal sheet resistance. Within this paper, the effects of three different resist rework strip procedures on subsequent TiN hard mask and dual damascene etching, using O2, H2N2 and H2O plasma processes, are compared. Furthermore, the interaction of the rework process with the CD tuning capabilities in dual damascene etch are evaluated. Summarizing the data, a stable process flow for wafers with and without resist rework is shown, eliminating litho CD rework offsets, resulting in metal trench processing with tight geometrical and electrical distributions.
Grayscale lithography has become a common technique for three dimensional structuring of substrates. In order to make the process useful for manufacturing of semiconductor and in particular optoelectronic devices, high reproducible and uniform final film thicknesses are required. Simulations based on a calibrated resist model are used to predict customized process parameters from pixel layout to 3d substrate patterning. Multiple, arbitrary resist heights are reached by using i-line lithography. Scalable and uniform transfer of discrete step heights into oxide are realized by multiple alternating high selective resist and oxide (MASO) etch. Requirements and limitations of reliable 3D film thickness and uniformity control within a CMOS fabrication environment are being discussed.
In this paper we describe an approach for the realization of 3D resist patterns for implant applications, highlighting the opportunities of controlling doping depth and profiles and their influence on device parameters. We choose a grayscale litho process, where the 3D structuring of the photoresist is done by a spatially variable exposure. Pixilated grayscale mask structures are defined to achieve the desired 3D resist patterns by locally variable transmittance values. The variable transmittance values result in different resist film thicknesses after development. Up to 20 different resist film thicknesses are obtained within a single exposure shot. This enables spatial patterning of the implant depth and accordingly various novel approaches for device optimization.
The fabrication of semiconductor devices can be complicated by various defectivity issues with respect to fabrication
process steps, their interactions, the used materials and tool settings. In this paper we will focus on a defect type, called
spire or cone defect. This conducting defect type is very common in the shallow trench isolation (STI) process. The
presence of a single defect can be responsible for a device breakdown or reliability problems, which will result in a
serious impact on the competitive edge for a product qualification. Spire defects, which can only be detected after etch,
are observed on all our technology nodes using 248nm or 193nm exposure techniques.
Bottom Anti-Reflection Coatings (BARC) impurities are considered to be the main root cause for the formation of spire
defects. Therefore we focused our efforts on chemical filtration of the BARC material and related solvents, the usage of
different BARC materials and the influence of the subsequent etch steps in order to reduce or overcome the spire defect
problem. In this paper we will discuss the effectiveness of different filter materials, pore sizes and different BARC
materials (organic and dielectric BARC) with respect to defect analysis and lithographic performance.
Among available lithography resolution enhancement techniques the Selective Inverse Lithography (SILT) approach
recently introduced by authors  has been shown to provide the largest process window on lower-NA exposure tools
for 65nm contact layer patterning. In present paper we attempt to harness the benefits of source mask optimization
(SMO) approach as part of our hybrid RET. The application of source mask optimization techniques further extends the
life-span of lower-NA 193nm exposure-tools in high volume manufacturing. By including SMO step in OPC flow, we
show that model-based SRAF solution can be improved to approach SILT process variation (PV) band performance.
Additionally to OPC, the complexity of embedded flash designs requires a high degree of exposure tool matching and a
lithography process optimized for topographically different logic and flash areas. We present a method how SMO can be
applied to scanner matching and topography-related optimization.
In order to fulfill the demands of further shrinkage of our mature 90nm logic litho technologies under the constraints of
costs and available toolsets in a 200mm fab environment, a project called "Push to the Limits" was started. The aim ís
to extend the lifetime and capabilities of existing dry 193nm litho toolsets with medium to low numerical aperture,
coupled with the availability of materials and processes which were known to help up CD miniaturization and to shrink
the 90nm logic litho process as far as possible. To achieve this, various options were explored and evaluated, e.g.
optimization of illumination conditions, evaluation of new materials, usage of advanced RET techniques (OPC, LfD,
DfM and ILT) and resolution enhancement by chemical shrink (RELACS®). In this project we demonstrate how we were
able to extend our existing 90nm technology capability, down close to 65nm node litho requirements on most critical
layers. We present overall result in most critical layer generally and specifically on most difficult layer of contact.
Typical contact litho target at 100nm region was enabled, while realization of 90nm ADI target is possible with addition
of new process materials.
With escalating costs of higher-NA exposure tools, lithography engineers are forced to evaluate life-span extension of
currently available lower-NA exposure tools. In addition to common resolution enhancement techniques such as off-axis
illumination, edge movement, or applying sub-resolution assist features, Inverse Lithography Technology (ILT) tools
available commercially at this moment offer means of extending current in-house tool resolution and enlarging process
window for random as well as periodic mask patterns. In this paper we explore ILT pattern simplification procedures and
model calibration for a range of illumination conditions. We study random pattern fidelity and critical dimension
stability across process window for 65nm contact layer, and compare silicon results for both conventional optical
proximity correction and inverse lithography techniques.
The growing importance of mask simulation in a low-k1 realm is matched by an increasing need for numerical methods
capable of handling complex 3D configurations. Various approximations applied to physical parameters or boundary
conditions allowed a few methods to achieve reasonable run-times. In this work the theoretical foundation and
simulation results of an alternative 3D mask modeling method suitable for OPC simulations are presented. We have
established the throughput and accuracy of the Coupled-Dipole Simulation Method and have compared results to the
rigorous FDTD approach using a test pattern. We will discuss in detail possible approximations needed in order to
accelerate the method's performance.
Including etch-based empirical data during OPC model calibration is a desired yet controversial decision for OPC
modeling, especially for process with a large litho to etch biasing. While many OPC software tools are capable of
providing this functionality nowadays; yet few were implemented in manufacturing due to various risks considerations
such as compromises in resist and optical effects prediction, etch model accuracy or even runtime concern. Conventional
method of applying rule-based alongside resist model is popular but requires a lot of lengthy code generation to provide
a leaner OPC input. This work discusses risk factors and their considerations, together with introduction of techniques
used within Mentor Calibre VT5 etch-based modeling at sub 90nm technology node. Various strategies are discussed
with the aim of better handling of large etch bias offset without adding complexity into final OPC package. Finally,
results were presented to assess the advantages and limitations of the final method chosen.
CD requirements for advanced photomasks are getting very demanding for the 100 nm-node and below; the ITRS roadmap requires CD uniformities below 10 nm for the most critical layers. To reach this goal, statistical as well as systematic CD contributions must be minimized. Here, we focus on the reduction of systematic CD variations across the masks that may be caused by process effects, e.g. dry etch loading.
CD requirements for advanced photomasks are getting very demanding for the 100 nm-node and below; the ITRS roadmap requires CD uniformities below 10 nm for the most critical layers. To reach this goal, statistical as well as systematic CD contributions must be minimized. Here, we focus on the reduction of systematic CD variations across the masks that may be caused by process effects, e.g. dry etch loading. We address this topic by compensating such effects via design data correction analogous to proximity correction. Dry etch loading is modeled by gaussian convolution of pattern densities. Data correction is done geometrically by edge shifting. As the effect amplitude has an order of magnitude of 10 nm this can only be done on e-beam writers with small address grids to reduce big CD steps in the design data. We present modeling and correction results for special mask patterns with very strong pattern density variations showing that the compensation method is able to reduce CD uniformity by 50-70% depending on pattern details. The data correction itself is done with a new module developed especially to compensate long-range effects and fits nicely into the common data flow environment.