For the innovation of DRAM and Logic semiconductors, EUV lithography and mask technology have played a crucial role. This paper shifts the focus of technological innovation research from a business-centric view to an in-depth examination of both technology development and innovation processes in the EUV mask industry. It covers trends in lithography technology, the significance of EUV lithography, and advancements and evolution in EUV mask technology. The study highlights the characteristics of the EUV mask industry and its ecosystem of leading companies, analyzes previous research on the challenges and risks faced by these companies, and investigates the competition between established and emerging technologies. Using survey responses from senior managers of seven leading companies, the paper uncovers factors contributing to successful innovation within the EUV mask industry. It also explores future considerations for the EUV mask sector and potential collaborative strategies within its ecosystem.
High-resolution EUV mask patterning capability has been one of the key factors to enable sub-10nm nanofabrication. Especially, the emergence of the Multi-Beam Mask writer (MBMW) in photomask lithography was a breakthrough for achieving the write time independent of pattern complexity with fine resolution, opening the EUV era. However, as the transition towards high-NA EUV technology is ongoing to extend Moore’s law beyond 2nm-node and over, the novel exposure system challenges photomask manufacturing for higher resolution, accurate patterning fidelity and higher overlay due to 40% reduced resolution limit. Therefore, development of photomask lithography technologies including improved mask writer, photoresist, new materials of the substrate, and optimized EUV process is necessary to meet the desired minimum feature size and local fidelity such as local CDU, line edge roughness (LER) etc. In this paper, we aim to establish the evaluation method for optimized photomask process in upcoming high-NA EUV era. We analyze the budget of each factor contributing to EUV mask patterning performance including locality and resolution, and evaluate the total process window using MBMW. Finally, we discuss the comprehensive requirements and strategies on MBMW technology and relevant process to satisfy the mask patterning in the next generations from EUV mask maker's point of view.
As the design rule continues to shrink towards the EUV lithography and beyond, the EUV mask inspection is one of the most important technologies for HVM lithography. Until now, most of the EUV mask inspection was performed by the DUV inspection tools. However, due to the nature of 193nm source, the DUV inspection has resolution limit and is unable to perform through-pellicle inspection. To overcome these limitations, the actinic tool was proposed to achieve high-resolution pattern imaging performance and inspection sensitivity. As a result, the EUV imaging resolution of tested pattern such as DRAM and Logic design was improved by 4.7 times compared to DUV resolution and it can achieve the high-resolution inspection for the extreme OPC type pattern and SRAF pattern. While studies on EUV inspection algorithm was mainly focused on masks for logic devices, we developed the EUV mask inspection technology for DRAM and LOGIC devices with Lasertec ACTIS 150 tool. By using the 13.5nm EUV wavelength the APMI can selectively detect printable defects and reduce the detection of nuisance and false defects. Overall, the defect classification of APMI inspection can be easily done hence the higher-resolution imaging performance. We also applied machine-learning based DB inspection algorithm to overcome resolution limit and accuracy of conventional DB modeling based DUV mask inspection. Finally, by using the 13.5nm actinic source, we acquired the technology to detect phase defect and perform through-pellicle inspection.
As wafer manufacturing shrinks size and pitch of features, and EUV lithography introduces high NA, the control of photomask pattern placement error that contributes to wafer overlay becomes a critical requirement for leading-edge devices. For sub-3nm node devices, the pattern complexity has increased and the exposure dose has also risen due to the use of low-sensitivity resist. Accordingly, to improve the pattern fidelity and reduce the exposure time, masks are manufactured using Multi-Beam Mask Writer (MBMW). As a result of analyzing the mask pattern placement error budget for the main EUV resist of sub-3nm node device, e-beam resist charging was found to be the most significant factor. This is primarily due to the inability to use a charging dissipation layer (CDL), caused by defect issues and degradation of critical dimension (CD) linearity. In this paper, we conduct an in-depth analysis of mask pattern placement errors induced by the charging effect in the MBMW and present a charging control methodology to mitigate these pattern-density-dependent errors. We test the charging effect reduction, an integrated solution of hardware and software for charging control in the MBMW, and showcase its performance for two resists. When applied to mass productions, the charging effect correction (CEC) significantly reduces mask pattern placement errors in a single cell and improves mask overlay between two critical layers aligned in an overlay alignment scheme. Ultimately, this leads to a reduction of wafer in-field overlay error.
Multibeam mask writers(MBMW) have been rapidly occupying on the field of leading edge EUV mask patterning for last several years. Thanks to outstanding ability of MBMW characteristics, sophisticated mask patterns and higher local pattern fidelity with low sensitivity E-beam resist can be realized in EUV era. Now most mask makers want to make good use of MBMW as a standard of making high-end grade masks such as Memory, Logic chips and etc. For this reason, they require higher pattern accuracy, faster writing time, higher data handling efficiency and matured machine stability aiming for the innovative mask making environment. Moreover, Larger coverage is needed as well not only for Low/High-NA EUV masks but also for even ARF masks.
In this paper, we touch key items with regard to comprehensive requirements from the mass production's point of view, for the versatile machines, several works and challenges to overcome on MBMW will be discussed.
With continued design shrinks enabled by EUV lithography, there is a greater need for high sensitivity reticle inspections to minimize defectivity during reticle manufacturing. While laser-illumination based inspection systems have been the workhorses in reticle quality control so far, electron-beam based inspection systems have fundamentally been expected to provide the highest resolution needed for the most critical layers. To address this EUV inspection need at the 3x nm pitch and beyond, KLA has developed a multi-column e-beam inspection system. This new e-beam inspector provides the industry’s highest sensitivity die-to-database inspection system and is based on a unique multi-column e-beam architecture for HVM-worthy throughput. With multiple systems shipped to address gap layers at leading-edge mask shops, this new system has demonstrated significant sensitivity advantages while overcoming the long-standing e-beam limitation of throughput gap vs. optical systems. This paper covers the technology that combines advantages of e-beam resolution with KLA’s database inspection algorithms. Additionally, recent inspection results are reviewed, highlighting the sensitivity results.
Extreme Ultraviolet (EUV) mask has Critical Dimension (CD) errors from various kinds of sources. Those errors are controlled for and corrected by proper correction methods such as fogging effect correction (FEC), loading effect correction (LEC), proximity effect correction (PEC), mask process correction (MPC) and so on. The corrections are mostly done independently. For example, conventionally CD nonlinearity has been the scope of mask process correction (MPC) and proximity effect has been that of proximity effect correction (PEC) because the interaction range considered is different from each other. But in order to improve the CD quality, we may need to consider the residual errors of PEC in MPC as well. For this purpose, we evaluated a new MPC method, named PEC-aware MPC, which considers writer's internal PEC for both model optimization and correction.
With the introduction of the multi-beam mask writing (MBMW) technology, efficient processing and precise patterning of curvilinear mask shapes are becoming increasingly important due to the wafer lithography advantages associated with the shapes. However, as the complexity of the curvilinear mask shapes increases, it becomes difficult to precisely characterize the curvilinear mask shapes. Barrier to this is prediction and reflection of the nature of curvilinear mask shapes. Therefore, in the industry, a novel algorithm method for accurate patterning is a major concern. In this study, we discuss the status of curvilinear mask shapes and patterning technology. By adopting machine learning, we develop a novel algorithm with considering the nature of curvilinear mask shapes. To evaluate practical use and accuracy of model, we demonstrate that the algorithm has significant value to guarantee the mask critical dimension (CD).
Curvilinear pattern has been introduced as one of solutions for complex and challenging next generation lithography. However mask process correction (MPC) has been developed originally for Manhattan pattern. MPC now is using only orthogonal CD measurement information (so-called conventional modeling) which is not sufficient to represent all information needed to curvilinear pattern. In this reason a new solution for MPC is required for curvilinear pattern. Contour modeling is one of the known modeling techniques, which uses information of many vertices along pattern contour instead of orthogonal CD values. However contour modeling has not been evaluated yet in mass production level. As an evaluating procedure, we introduce a quality assurance (QA) method using virtual SEM contour. By adopting this QA method, we can analyze errors only from modeling itself separated from process induced errors. Moreover, aspect of error budget can be estimated by adding various errors on purpose. In this paper, we present the QA results of contour modeling and the comparison to the conventional modeling. Some discussion and future works will be followed.
In extreme ultra violate(EUV) era, the resolution is highly improved by its shorter wavelength than ArF lithography. That changes double patterning technology(DPT) or quadratic pattering technology(QPT) process by ArF to single exposure technology(SET) process by EUV. But the number of EUV photons that have same amount of energy in unit area is reduced by 10 times more than that of ArF photons, and it occurs stochastic effect like random bridge and necking defects. In other words, one EUV photon has larger energy than one ArF photon, but the unstable probability to transfer its energy to photo resist(PR) induces the lack of active energy or more of it so that results in the random defects1 . To minimize this problem, it is needed to improve normalized image log slope(NILS). Introducing curvilinear pattern is one of the techniques improves NILS and it seems that optical proximity correction(OPC) is ready for producing them. But for their high complexity, the difficulties of actual implementation on mask are remained. In the paper, we will announce the several difficulties and requirement to raise the maturity for curvilinear pattern mask fabrication.
For the era of multi-beam mask writer, in the 2019 BACUS conference, we proposed the formation of a data format working group to address the need for curvilinear data representation. The new working group was formed in October 2019 driven by major semiconductor companies with representations from Mentor, Synopsys, Nippon Control Systems, D2S, Aselta, and ASML-BRION with the initial goals to quantify the curvilinear data volume problem; develop, test and implement new or revised formats based on OASIS; and to formalize the working group as a SEMI task force (TF). In this paper, the necessity of a new curvilinear data format and the progress of our TF will be introduced. Furthermore, we demonstrate that given the nature of curvilinear data, representing it using native curve formats has significant value to reduce file size for future mask making flows.
Inverse lithography technology (ILT) optical proximity correction is going to play a critical role in addressing challenges of optical and EUV lithography as the industry pushes toward advanced nodes. One major barrier in adoption of ILT has been the mask writer’s inability to efficiently write curvilinear patterns. With the introduction of multibeam mask writers, this barrier has been removed and widespread adoption of ILT is imminent. Traditionally, mask writers have accepted only trapezoidal inputs to the tool, though recent trends show that mask writers are adopting newer formats that already reduce file size. However, as the ILT shape complexity and data volume increases further for 5 nm nodes and beyond, the explosion of mask pattern data file size becomes a major concern. Therefore, there is a need for the industry to look toward other compact formats of data representation that will be capable of serving well for multiple generations of mask making. We compare various curvilinear data representation schemes and their value in the curvilinear ILT-based mask manufacturing flow. We demonstrate that given the nature of curvilinear data, representing it using native curve formats has significant value to reduce file size for future mask making flows. The same format may not be applicable for all types of features in the input mask. These options will be discussed. We will compare the value of such exotic representations with regular simplification approaches that reduce data volume using standard methods and discuss the extents and limits of all these techniques. To evaluate practical use of curvilinear representation in place of conventional piecewise linear representation, we manufacture and measure a photomask to evaluate the accuracy of curvilinear representations. Finally, we use EUV AIMS to assess the impact of curvilinear representation on wafer process window.
Multi-beam mask writers (MBMW) offer the potential to enable the use of ideal curvilinear shapes for ILT masks, but current layout formats are not sufficient to represent complex ILT designs efficiently from OPC through mask making.
In the 2019 BACUS conference, we proposed the formation of a data format working group to address the need for curvilinear data representation for MBMW. The Curvilinear data format working group was first initiated in October 2019 with participation from EDA companies and advanced mask makers.
In this paper, the necessity of a new curvilinear data format and our working group will be introduced. We will discuss the progress and the plan of the working group.
Data technology for data handling, correction, and verification has become the essential technology of photomask. By the shrinkage of device pitch and the development of lithography technology, the data volume of photomask has been increased continuously and the correction and verification technology based on design data has an important role to meet the target of patterning quality. Especially, because EUV lithography makes single patterning possible, the decrease of device pitch rises to the challenge on the data technology for EUV photomask. Furthermore, the multi-beam mask writer which enables dose modulation for each pixel requires fundamental changes such as data format, data flow, and correction algorithm. Here, we will discuss about 7 kinds of data technologies and one proposal for the era of EUV lithography.
Multi-beam mask writer MBM-1000 is developed for N5. It is designed to accomplish higher throughput than a singlebeam
VSB writer EBM-9500 at shot count higher than 500 G/pass, and write masks with low sensitivity resist to have
better CDU and patterning resolution. Product version of blanking aperture array (BAA) for MBM-1000 is fabricated
along with data transfer system to accomplish data rate of 300 Gbps. They have been integrated with writing control
software based on MBF format, a tool-specific format which handles any-angle pattern and polygon patterns. Writing
test without re-adjustment of beam current showed that exposure time control by BAA blanking is very stable, and linear
CD drift is less than 0.1 nm for 10 hours. Complex OPC pattern and ring pattern were printed on low-sensitivity pCAR
resist and showed good resolution to resolve 25 nm isolated line.
Multi-beam mask writer is under development to solve the throughput and patterning resolution problems in
VSB mask writer. Theoretically, the writing time is appropriate for future design node and the resolution is
improved with multi-beam mask writer. Many previous studies show the feasible results of resolution, CD
control and registration. Although such technical results of development tool seem to be enough for mass
production, there are still many unexpected problems for real mass production.
In this report, the technical challenges of multi-beam mask writer are discussed in terms of production and
application. The problems and issues are defined based on the performance of current development tool
compared with the requirements of mask quality. Using the simulation and experiment, we analyze the specific
characteristics of electron beam in multi-beam mask writer scheme. Consequently, we suggest necessary
specifications for mass production with multi-beam mask writer in the future.
As the integration node becomes smaller in 193nm ArF immersion optical lithography, the complexity of optical proximity correction (OPC) has been increased continuously. Moreover, pattern design should be changed by more aggressive transformation technique such as inverse lithography technique (ILT). The greater fidelity to the target design on wafers is achieved by the application of these OPC techniques and results in the greater complexity level of the mask patterns. Complicated mask pattern consists of many corners and assist features, which raises the fraction of small shots in e-beam data. To get more accurate mask pattern, the dose stability of small shots becomes more important in a complicated mask pattern. In this paper, we present the evaluation results of the small shot handling capabilities of e-beam machines. According to the results, the information of small shots generated during data fracturing should be considered as a factor that defines the complexity of patterns in e-beam writing. It shows that the small shot printing in e-beam machines need to be improved in order to guarantee mask pattern quality.
To overcome the resolution and throughput of current mask writer for advanced lithography technologies, the platform of e-beam writer have been evolved by the developments of hardware and software in writer. Especially, aggressive optical proximity correction (OPC) for unprecedented extension of optical lithography and the needs of low sensitivity resist for high resolution result in the limit of variable shaped beam writer which is widely used for mass production. The multi-beam mask writer is attractive candidate for photomask writing of sub-10nm device because of its high speed and the large degree of freedom which enable high dose and dose modulation for each pixel. However, the higher dose and almost unlimited appetite for dose modulation challenge the mask data processing (MDP) in aspects of extreme data volume and correction method. Here, we discuss the requirements of mask data processing for multi-beam mask writer and presents new challenges of the data format, data flow, and correction method for user and supplier MDP tool.
Recently, Multi-Beam Mask Writer (MBMW) scheme is newly considered for next generation writing scheme. As the
MBMW writing uses many multi-array bundle beams with small spot size, the fast writing and complex pattering is
possible conceptually.
The target dose level of MBMW is high around 100μC/cm2 and the target of total writing time is within 10 hours for
next generation layout with complex and small node pattern. The risks of high dose writing are rising of blank
temperature, chemical reaction with photo-resist and charging effects in blank. In addition, the fast writing can cause the
rising of temperature in blank.
The heating effect can be divided into local and global terms, and each effect of critical dimension (CD) and
registration was analyzed by heating effect. In case of MBMW, the global heating is more critical than local heating.
Therefore, we need to study about the global heating effect which can affect global registration in MBMW.
In this paper, we study about the global heat distribution on mask blank in certain MBMW writing condition, and the
directional deformation of blank which can affect global registration was analyzed by using Finite Element Method
(FEM). We approach with two kinds of modified heat model and the FEM model was verified with analytical calculation.
The temperature variation and deformation distribution were achieved with transient method with the writing
conditions, in case of 100μC/cm2 of total dose, 50kV of acceleration voltage, 100% of chip density and 10 hour of total writing time. Therefore, we can consider the writing conditions according to mask specification in MBMW scheme.
Optical design of an image magnifier based on a lens array is presented. The proposed image magnifier does not have a limit for object size due to off-axis aberration because the object is divided into segments and is kept apart from the nearest neighbor segment with the period of the lens array. Several images can be sequentially generated by magnifying sequentially specific objects among mosaic objects, which are composed of multi-images. The designed lens for the image magnifier corresponds to a lens array with an aperture of 2 mm and a magnification ratio of 3. Furthermore, an application for a display system of the designed image magnifier is also presented.
Because mask patterning quality of CD uniformity, MTT, registration and smaller assist feature size is important for wafer patterning, the higher exposure dose and complex pattern design will be necessary. It is the reason why the faster and more accurate e-beam mask writer is needed for future design node. Multi-beam mask writer is the most promising new e-beam mask writer technology for future sub-10nm device mask patterning to solve the pattern quality issue and writing time problem. In this report, the technical challenges of multi-beam mask writer are discussed by comparison with problems of current VSB e-beam mask writer. Comparing with e-beam mask writer which has the critical issues of beam size and position control, the application of entirely different methods and techniques of CD and position control is essential for multi-beam mask writer which has new architecture and writing strategy. Using the simulation method, we present the different challenges between VSB and multi-beam mask writer. And there are many important technical requirements to achieve expected specification of multi-beam mask writer. To understand such requirements, the patterning simulation and mathematical calculation are done for analysis. Based on the patterning simulation, the detail technical requirements and issues of multi-beam mask writer are achieved. Consequently, we suggest the direction of multi-beam mask writer development in terms of technical challenges and requirements.
A refractive beam shaper is designed, which transforms a Gaussian beam profile into a diverging uniform line beam profile, exactly, an elongated super-Gaussian profile. The advantage of our optical system is that the area of uniform illumination can be changed by simply shifting the position of the observation plane without using an additional optical element. Whereas previous refractive beam shapers have been designed to have a specific intensity distribution at a certain position, our refractive beam shaper has been designed to generate a desired intensity and wavefront simultaneously, so that it gives a desired beam profile during propagation. The designed refractive beam shaper generates a uniform line beam with 4 mm beam width at half maximum intensity and a diverging angle of 13.3 deg. Furthermore, we have checked the utility and the stability of the output beam by calculating the changes in the size, the uniformity, and the efficiency of the line beam when it propagates a distance of 960 mm.
We present the limit of a conventional photomask writer and new possibilities to meet various requirements of tight specifications for a sub-10 nm device. The issues of a variable shaped beam (VSB) writer and how to overcome the limit by computational techniques are discussed. Because VSB writing can use only one rectangular or triangular beam per shot, the complex design for computational lithography results in the increase of shot number to implement rounded or angled pattern. Based on model-based-fracturing, we have confirmed that the ideal curvilinear pattern can be optimized by using overlapping shots, and that they have the same patterning performance in mask and wafer. On the other hand, the multibeam writer can make ideally any kinds of shapes, even curvilinear design because the combination of small spots writes a design. In a real situation, each spot of multibeam writer is defined at fixed mesh and each beam has discrete dose level, so that there are fidelity errors if the pixel size is large or the dose level is not enough large. Here, we propose a “Buddhist cross” design as the evaluation pattern of digitization error in a multibeam writer. The “fidelity error” smaller than 0.5 nm error requires 5 nm pixel size and the required minimum number for dose level is 7 to implement a smaller error than 0.05 nm at one edge. To realize new technology for mass production, new data flow, model based pattern verification, and required computing power have been presented.
Computational lithography, e.g., inverse lithography technique (ILT) and source mask optimization, is considered necessary for the “extremely low k1” lithography process of sub-20 nm device node. The ideal design of a curvilinear mask for computational lithography requires many changes during photomask fabrication. These range from preparation of the mask data to measurement and inspection. The manufacturability of a photomask for computational lithography is linked to predictable and manageable quality of patterning. Here, we have proposed the use of “inverse e-beam lithography” on photomask for computational lithography, which overcomes the patterning accuracy limits of conventional e-beam lithography. Furthermore, the preferred target design for ILT, a new verification method, and the accuracy required for the mask model are also discussed; with consideration of acceptable writing time (<24 h ) and computing power.
Magnetic Random Access Memory (MRAM) has emerged as the leading candidate for future universal memory due to its non-volatility, excellent endurance and read/write performance. The magnetic tunnel junction (MTJ) is a data storage element in MRAM and is basically composed of two ferromagnetic layers separated by the magnesium oxide (MgO) tunnel barrier. MgO between two ferromagnetic layers was adopted to enlarge the resistance difference between two kinds of magnetic arrangements by tunneling current through MgO. Like this, it is important to understand characterization of MgO for developing Mram. Due to thin thickness of MgO, FIB milling should be used for the preparation of TEM specimens in Mram. The major problem in MgO sampling by FIB milling is the transform of MgO between two ferromagnetic due to FIB induced damage, which leads to high tunnel current through MgO and high resistance difference between two kinds of magnetic arrangements. An understanding of FIB generated artifact on MgO is important to analysis Mram and to optimize the sample preparation process. The normal ion beam damage are compared with low-keV FIB ion beam damage on blanket MgO wafer. Experiments were performed using Helios 450 FIB(FEI) and XV-200TBs(SII) with gallium ion sources operated at 30 keV to 2 keV, respectively. As a preliminary, the thicknesses of all specimens were fixed at 100nm for the final ion beam milling currents of 210 pA(30 keV) by Helios 450 FIB(FEI). Specimens of 100nm were transferred to low-keV FIB (Helios 450/XV-200TBs) to do the low-keV ion milling. Then each specimen had a 2 keV cleaned surface and a 30 keV FIB prepared surface. In this paper, we understand the normal ion beam damage on blanket MgO through changing beam current and beam voltage. Then we present the optimized recipe and which equipment is better to analysis.
The computational lithography such as inverse lithography technique (ILT) or source mask optimization (SMO) is considered as the necessary technique for the extremely low k1 lithography process of sub-20nm node. The ideal curvilinear mask design for computational lithography gives the impacts and requires many changes on the photomask fabrication from mask data preparation to measurement and inspection. In this paper, we present the current status and new requirements for the computational lithography mask in viewpoint of the manufacturability for mass production. The manufacturability of computational lithography mask can be realized by the predictable and manageable patterning quality. Here, we have proposed new data flow for ILT which covers what the preferred target design is for ILT, new verification method, required mask model accuracy, and resolution improvement method. Furthermore, considering acceptable writing time (<24 hours) and computation limit on convolution, the current ILT technique is shown to have the limit of application area.
Mask Error Enhancement Factor (MEEF) has been a standard measure of mask quality [1]. One of the key
assumptions in the construction of MEEF is that mask CD uniformity is not dependent on the shape of mask
feature and can be considered to be a constant for given mask process. This assumption is no longer valid for
small (<100nm), curvilinear or diagonal features. In this paper we extend definition of MEEF to be valid for all
mask shapes call new metric extended MEEF or eMEEF. We also demonstrate on the example of ILT features that
eMEEF increases predictability of mask and wafer CD uniformity sometimes changing overall conclusion about
mask/wafer manufacturability.
Model-Based Mask Data Preparation (MB-MDP) has been discussed in the literature for its benefits in reducing mask
write times [1][2]. By being model based (i.e., simulation based), overlapping shots, per-shot dose modulation, and
circular and other character projection shots are enabled. This reduces variable shaped beam (VSB) shot count for
complex mask shapes, and particularly ideal ILT shapes [3]. In this paper, the authors discuss another even more
important aspect of MB-MDP. MB-MDP enhances CD Uniformity (CDU) on the mask, and therefore on the wafer.
Mask CDU is improved for sub-80nm features on mask through the natural increase in dose that overlapping provides,
and through per-shot dose modulation. The improvement in CDU is at the cost of some write times for the less complex
EUV masks with only rectangular features. But these masks do not have the basis of large write times that come from
complex SRAFs. For ArF masks for the critical layers at the 20nm logic node and below, complex SRAFs are
unavoidable. For these shapes, MB-MDP enhances CDU while simultaneously reducing write times. Simulated and
measured comparison of conventional methodology and MB-MDP methodology are presented.
As semiconductor features shrink in size and pitch, the extreme control of CD uniformity, MTT and image placement
is needed for mask fabrication with e-beam lithography. Among the many sources of CD and image placement error,
the error resulting from e-beam mask writer becomes more important than before. CD and positioning error by e-beam
mask writer is mainly related to the imperfection of e-beam deflection accuracy in optic system and the charging and
contamination of column. To avoid these errors, the e-beam mask writer should be designed taking into account for
these effects. However, the writing speed is considered for machine design with the highest priority, because the e-beam
shot count is increased rapidly due to design shrink and aggressive OPC. The increment of shot count can make the
pattern shift problem due to statistical issue resulting from e-beam deflection error and the total shot count in layout.
And it affects the quality of CD and image placement too.
In this report, the statistical approach on CD and image placement error caused by e-beam shot position error is
presented. It is estimated for various writing conditions including the intrinsic e-beam positioning error of VSB writer.
From the simulation study, the required e-beam shot position accuracy to avoid pattern shift problem in 22nm node and
beyond is estimated taking into account for total shot count. And the required local CD uniformity is calculated for
various e-beam writing conditions. The image placement error is also simulated for various conditions including e-beam
writing field position error. Consequently, the requirements for the future e-beam mask writer and the writing
conditions are discussed. And in terms of e-beam shot noise, LER caused by exposure dose and shot position error is
studied for future e-beam mask writing for 22nm node and beyond.
By the development of double exposure technique and the EUV lithography the pattern placement error of photomask is
interested because of its impact on size and position of wafer pattern. Among various sources to induce the pattern
placement error, we have focused on the resist charging effect and shown that the resist charging effect generates pattern
position error and CD variation. Based on experiment and simulation, we present quantitatively the dependence of
position error on pattern density, pattern shape, and writing order. Furthermore, we have discussed the model to describe
the charging effect and its agreement with experiment, and correction method to remove the resist charging effect.
KEYWORDS: Photomasks, Extreme ultraviolet, Scattering, Monte Carlo methods, Ray tracing, Electron beam lithography, Molybdenum, Metals, Ion beams, Laser scattering
The ray tracing of electron based on Monte Carlo is simulated by GEANT software to investigate the electron scattering
property in ArF photomask and EUV photomask. By Monte Carlo simulation, we have presented the mechanism of
electron scattering in EUV photomask and simulated the electron distribution which gives rise to change the patterning
performance of EUV photomask, compared with those of ArF photomask. Furthermore, the overlay error of EUV
photomask has been analyzed by the charging model.
EUV photomask has the additional electron distribution in the range of 2um, which comes from the strong electron
scattering at Mo/Si multilayer. Because of this additional electron distribution, EUV photomask has the pattern size
error due to proximity effect of electron when the conventional Gaussian function is used to correct the proximity effect
of ArF photomask. The maximum residual error due to the proximity effect in EUV photomask is 7nm. Furthermore, we
have confirmed that the linearity of pattern size is so different from ArF photomask and it is well explained with the
Gaussian blur model based on the electron distribution of EUV photomask.
In mask fabrication, e-beam exposure equipment malfunctioning could produce erroneous masks, several consecutive
mask failures in the worst case. This type of error might unexpectedly increase mask turnaround time. Due to high
cost of mask fabrication and its annual growth, it is critical detecting those errors as early as possible. Since mask SEM
images at after-development inspection (ADI) phase have more visible noise, edges might be hard to detect clearly using
classical edge detection algorithms. In this context, we present a novel pattern error detecting algorithm to capture pattern
errors in mask monitoring patterns by inspecting mask SEM images at ADI phase. The originality of this paper lies
in its use of simple but powerful techniques in a series used for automated error detection. More specifically, we inspect
two specific types of errors in SEM images of monitoring patterns: bridging errors in a chessboard pattern, and CD uniformity
errors in a line-and-space pattern. For a chessboard pattern, we utilize both horizontal and vertical projections of
image intensity histogram to find areas for inspection automatically. From one dimensional projection of the image, we
identify spatial coordinates of our interests, and define a small rectangular region, called D-region. For each D-region,
we determine whether a pattern bridge is likely to occur, based on the ratio of brighter pixels in it. For a line-and-space
pattern, we compute base lines for CD measurement, and detect CD uniformity errors or line shift errors by applying
similar one dimensional histogram analysis and CD-computation algorithm to the image. Our experimental results using
real pattern images and programmed defect images support that this technique is effective and robust in detecting errors
without layout data or another SEM image for comparison.
As semiconductor features shrink in size and pitch, there are strong needs for an advanced mask writer which has better
patterning quality. Among various requirements for next photomask writer, we have focused on the requirements of ebeam
size and position accuracy for hp 32nm and beyond generation.
At the era of DPT, EUV, and complex OPC, the photomask is required to have extreme control of critical dimension
(CD). Based on simulation and experiment, we present the e-beam requirements for advanced mask writer, in view
point of stability and accuracy. In detail, the control of e-beam size in mask writer should be decreased to 0.5nm
because the size error of e-beam gives rise to large CD error according to the high complexity of mask pattern.
Furthermore, the drift error of beam position should be smaller than 1nm to obtain the tight pattern placement error and
to minimize the edge roughness of mask pattern for the era of computational lithography and EUV lithography.
As semiconductor features shrink in size and pitch, the extreme control of CD uniformity and MTT is needed for
mask fabrication with e-beam lithography. And because of huge shot density of data, the writing time of e-beam
lithography for mask fabrication will be increased rapidly in future design node.
The beam drift caused by charging of optic system and current density drift can affect the beam size, position and
exposure dose stability. From the empirical data, those are the function of writing time. Although e-beam lithography
tool has the correction function which can be applied during writing, there are remained errors after correction which
result in CD uniformity error. According to the writing time increasing, the residual error of correction will be more
important and give the limit of CD uniformity and MTT.
In this study, we study the beam size and exposure dose error as a function of time. Those are mainly caused by
charging and current density drift. And we present the predicted writing time of e-beam lithography below 32nm node
and estimate its effect on CD control error. From the relation between writing time and CD control error, we achieve the
limit of CD uniformity with e-beam mask writer. And we suggest the method to achieve required CD uniformity at
22nm node and beyond.
In extreme ultraviolet lithography (EUVL), mask non-flatness contributes to overlay errors in EUVL scanners. Tight
non-flatness targets are required to meet future overlay; for example, the International Technology Roadmap for
Semiconductors (ITRS) requires that substrate non-flatness will need to decrease to 36 nm peak-to-valley in 2013. To
meet these tight non-flatness values, suppliers must use aggressive polishing steps, adversely impacting substrate yield
and mask blank cost of ownership. An alternative option is to use image placement corrections at the writing step of the
reticle to compensate for the predicted impact of the non-flatness pattern placement errors, which would allow the
specifications to be relaxed.
In this paper, we will present the results of using e-beam image placement corrections during mask writing to
compensate for mask non-flatness. A low thermal expansion material (LTEM) substrate with about 500 nm of nonflatness
was employed. Three different compensation methods were used to calculate the predicted image placement
errors based upon the mask non-flatness, including the expected errors from scanner chucking. The mask was designed
to use a repeating set of four ASML alignment marks (XPA marks) across the mask. During e-beam writin, one mark
was left uncompensated, and the three different compensation methods were applied to the remaining marks. The masks
were exposed using the ASML alpha demo tool (ADT). An overview of the viability of e-beam correction
methodologies to compensate for mask non-flatness is presented based upon the wafer overlay results.
Recent Low k1 era requires aggressive OPC technology with advanced lithography technology. The aggressive OPC
contains the rounded pattern and a lot of assistant pattern which are the main source to increase the shot division. We
have defined the shot complexity, which is defined by the ratio of number of shot between the interested pattern and the
1:1 L/S pattern. Based on shot complexity parameter, we have estimated the writing time as the device node decreases.
We expect that the aggressive OPC and the high dose could generate severely the writing time issue in 32nm node era.
As semiconductor features shrink in size and pitch, the image placement error at photomask has been interested as an
important factor to be reduced. Especially, by the development of double exposure technique (DET) or double
patterning technique (DPT) for sub-45 nm node the image placement error is required to be controlled tightly.
Following ITRS roadmap, when DET or DPT is used the registration for sub-45 nm node is required to be less than 4
nm but this specification still corresponds to the challengeable goal. Among various sources of image placement errors,
here, we focus on the error occurring at patterning process of photomask and discuss its effect on the photomask
overlay. We name the image placement error occurred at patterning process due to e-beam charging effect, absorber
etching effect, and so on as the pattern loading effect. We quantify the amount of pattern loading effect on registration
error, analyze it with the help of simulation and experiment, and discuss the character of each error and correction
method.
As semiconductor features shrink in size and pitch, the pattern placement error at photomask, that is, the registration
becomes more important factor to be reduced. Following ITRS roadmap, the registration for sub-45 nm node is required
to be less than 5 nm but this specification still corresponds to the challengeable goal. Among several reasons to induce
registration, here, we have focused on four major registration errors: e-beam positioning error, patterning effect, pellicle
attachment effect, and sampling error of measurement. We quantify and analyze each error with the help of finite
element modeling and by experiment. Based on these results, we present the current status and the goal of each error for
the roadmap of sub-45 nm node.
By numerical simulations, it has been shown that a conventional cylindrical rod can be used as a hollow conic beam generator by illuminating a parallel laser beam inclined to the axis of the rod. Half of the conic beam is formed by the reflection at the surface of the cylindrical rod, and the opposite side of the conic beam by its transmission. We discuss the parameters to determine the size of the conic beam and the effect of the dielectric multilayer coating on the intensity distribution of the conic beam. The line beams of the shapes such as circle, ellipse, parabola, or hyperbola can be generated by this hollow conic beam generator, depending on the position and orientation of the observing plane.
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