Optical encoding technology is one of the most popular technologies with nano-meter degree accuracy in precise displacement metrology field. Basically, two optical gratings overlap in the encoder, resulting in Moiré fringes. An optical sensor records the Moiré fringes signal. When one of the optical gratings moves, the Moiré fringes will vary. The phase of the Moiré fringes is extracted from the signal, and the displacement is obtained from the phase. The fabrication always becomes more difficult and the cost is higher when the measurement accuracy becomes higher for such optical encoder. We have developed a simple, novel encoder with only one optical grating and an optical imaging system. The Moiré fringe curve is obtained when the optical grating overlaps with two complementary digital gratings which are virtually constructed with a CCD or CMOS sensor in a camera. In this technique, the Moiré fringe curve is not a strict sine wave, leading to some difficulty to accurately extract the phase value. This paper compares the performance of four phase extraction algorithms, i.e., Fourier transform, polynomial fitting, Hilbert transform and wavelet transform. The experimental results show that both the measurement accuracy and repeatability of the four algorithms are within 30 nm after calibration. The overall accuracy of the wavelet transform is the best with minimum error of only 5 nm. The processing speed of FFT is the fastest, reaching sub millisecond level.
Scanning electron microscope (SEM) and its variations, such as critical dimension SEM (CD-SEM) and electron beam inspection (EBI-SEM), are getting increasingly critical in process control in very large-scale integration circuits (VLSI) manufacturing. For rapid capturing of image, the patterned wafer surface needs to be maintained in a range smaller than the depth of focus (DoF) of the electron beam. A triangulation optical system is used to sense the wafer surface for the rapid leveling of the wafer height in real time. An optical grating illuminated by a LED light source is projected onto the wafer and further imaged to a camera. The wafer height is calculated from the displacement of the optical grating image. However, pattern variation under the measurement area of the wafer may affect the transmission ratio of the light to the sensor and further the measurement accuracy. To achieve a high precision measurement result, an automatic light intensity adjustment system is developed. A computer records the optical grating image and the image intensity is analyzed. If the grating image intensity in the bright area is not in the desired range, a control software will convert the delta into the LED driving current increment or decrement, and the LED light output will be adjusted accordingly so that the image intensity is brought back to the expected range and keep there for the entire process. The LED feedback control experiment shows that the system remains at the target grey level without noticeable variation when the system transmission ratio varies by a factor of 7.5 times.
The oblique incidence of the illumination system in EUV lithography combined with relative thick absorber layer of EUV mask introduces many unique distortions on the image transfer between mask and wafer, most of these distortions are non-linear thus makes the enhancement of resolution more difficult. This paper focus on analysing the impacts of the absorber layer thickness, multilayer thickness and the light source morphology on the image. And improve the EUV lithography and imaging quality by co-optimization of these three parameters. Besides, the intrinsic features and rules of the impacts of absorber thickness on the imaging properties is revealed. And the different behaviour of 1D dense pattern and isolation pattern during the co-optimization is analysed and elucidated. This study provides a potential new direction for resolution enhancement technology.
For 1xnm node and beyond, even Extreme Ultraviolet Lithography (EUV) technology, the serious geometries distortions of the wafer patterns at new process are forcing chipmakers and foundries to utilize model-based SRAFs for ensuring the accuracy and manufacturability of the chips. Model-based Sub-Resolution Assistant Feature (SRAF) is based on inverse lithography (ILT), which is accurate but time-consuming. Therefore, it is necessary to extract the SRAF rules from model-based results and apply them to full chip layout. In this paper, we put forward a methodology of 2D SRAF rule extraction based on model-based results. We can describe and locate the SRAFs by introducing Projection Region, because it reflect the relationship between the SRAFs and main patterns. And the new concept Elongation can make the properties of SARFs more clearly. The experimental results show that the proposed method can extract the 2D SRAFs accurately and output the rules in a general format. The rule simplifying step can decrease the quantity of 2D SRAF rules through the identification and process of symmetry.