Many different advanced devices and design layers currently employ double patterning technology (DPT) as a means to overcome lithographic and OPC limitations at low k1 values. Certainly device layers with k1 value below 0.25 require DPT or other pitch splitting methodologies. DPT has also been used to improve patterning of certain device layers with k1 values slightly above 0.25, due to the difficulty of achieving sufficient pattern fidelity with only a single exposure. Unfortunately, this broad adoption of DPT also came with a significant increase in patterning process cost. In this paper, we discuss the development of a single patterning technology process using an integrated Inverse Lithography Technology (ILT) flow for mask synthesis. A single pattering technology flow will reduce the manufacturing cost for a k1 > 0.25 full chip random contact layer in a memory device by replacing the more expensive DPT process with ILT flow, while also maintaining good lithographic production quality and manufacturable OPC/RET production metrics.
This new integrated flow consists of applying ILT to the difficult core region and traditional rule-based assist features (RBAFs) with OPC to the peripheral region of a DRAM contact layer. Comparisons of wafer results between the ILT process and the non-ILT process showed the lithographic benefits of ILT and its ability to enable a robust single patterning process for this low-k1 device layer. Advanced modeling with a negative tone develop (NTD) process achieved the accuracy levels needed for ILT to control feature shapes through dose and focus. Details of these afore mentioned results will be described in the paper.
Aberration sensitivity matching between overlay metrology targets and the device cell pattern has become a common requirement on the latest DRAM process nodes. While the extreme illumination modes used demand that the delta in aberration sensitivity must be optimized, it is effectively limited by the ability to print an optimum target that will meet detectability and accuracy requirements. Therefore, advanced OPC techniques are required to ensure printability and have optimal detectability performance while maintaining sufficient process window to avoid patterning or defectivity issues.
In this paper, we have compared various mark designs with real cell in terms of aberration sensitivity under the specific illumination condition. The specific illumination model was used for aberration sensitivity simulation while varying mask tones and target designs. Then, diffraction based simulation was conducted to analyze the effect of aberration sensitivity on the actual overlay values. The simulation results were confirmed by comparing the OL results obtained by diffraction based metrology with the cell level OL values obtained using Critical Dimension Scanning Electron Microscope.
As the industry pushes to ever more complex illumination schemes to increase resolution for next generation memory and logic circuits, sub-resolution assist feature (SRAF) placement requirements become increasingly severe. Therefore device manufacturers are evaluating improvements in SRAF placement algorithms which do not sacrifice main feature (MF) patterning capability. There are known-well several methods to generate SRAF such as Rule based Assist Features (RBAF), Model Based Assist Features (MBAF) and Hybrid Assisted Features combining features of the different algorithms using both RBAF and MBAF. Rule Based Assist Features (RBAF) continue to be deployed, even with the availability of Model Based Assist Features (MBAF) and Inverse Lithography Technology (ILT). Certainly for the 3x nm node, and even at the 2x nm nodes and lower, RBAF is used because it demands less run time and provides better consistency. Since RBAF is needed now and in the future, what is also needed is a faster method to create the AF rule tables. The current method typically involves making masks and printing wafers that contain several experiments, varying the main feature configurations, AF configurations, dose conditions, and defocus conditions – this is a time consuming and expensive process. In addition, as the technology node shrinks, wafer process changes and source shape redesigns occur more frequently, escalating the cost of rule table creation. Furthermore, as the demand on process margin escalates, there is a greater need for multiple rule tables: each tailored to a specific set of main-feature configurations. Model Assisted Rule Tables(MART) creates a set of test patterns, and evaluates the simulated CD at nominal conditions, defocused conditions and off-dose conditions. It also uses lithographic simulation to evaluate the likelihood of AF printing. It then analyzes the simulation data to automatically create AF rule tables. It means that analysis results display the cost of different AF configurations as the space grows between a pair of main features. In summary, model based rule tables method is able to make it much easier to create rule tables, leading to faster rule-table creation and a lower barrier to the creation of more rule tables.
DRAM chip space is mainly determined by the size of the memory cell array patterns which consist of periodic memory cell features and edges of the periodic array. Resolution Enhancement Techniques (RET) are used to optimize the periodic pattern process performance. Computational Lithography such as source mask optimization (SMO) to find the optimal off axis illumination and optical proximity correction (OPC) combined with model based SRAF placement are applied to print patterns on target. For 20nm Memory Cell optimization we see challenges that demand additional tool competence for layout optimization. The first challenge is a memory core pattern of brick-wall type with a k1 of 0.28, so it allows only two spectral beams to interfere. We will show how to analytically derive the only valid geometrically limited source. Another consequence of two-beam interference limitation is a ”super stable” core pattern, with the advantage of high depth of focus (DoF) but also low sensitivity to proximity corrections or changes of contact aspect ratio. This makes an array edge correction very difficult. The edge can be the most critical pattern since it forms the transition from the very stable regime of periodic patterns to non-periodic periphery, so it combines the most critical pitch and highest susceptibility to defocus. Above challenge makes the layout correction to a complex optimization task demanding a layout optimization that finds a solution with optimal process stability taking into account DoF, exposure dose latitude (EL), mask error enhancement factor (MEEF) and mask manufacturability constraints. This can only be achieved by simultaneously considering all criteria while placing and sizing SRAFs and main mask features. The second challenge is the use of a negative tone development (NTD) type resist, which has a strong resist effect and is difficult to characterize experimentally due to negative resist profile taper angles that perturb CD at bottom characterization by scanning electron microscope (SEM) measurements. High resist impact and difficult model data acquisition demand for a simulation model that hat is capable of extrapolating reliably beyond its calibration dataset. We use rigorous simulation models to provide that predictive performance. We have discussed the need of a rigorous mask optimization process for DRAM contact cell layout yielding mask layouts that are optimal in process performance, mask manufacturability and accuracy. In this paper, we have shown the step by step process from analytical illumination source derivation, a NTD and application tailored model calibration to layout optimization such as OPC and SRAF placement. Finally the work has been verified with simulation and experimental results on wafer.
Model-driven target optimization using an ILT hotspot fixer is applied to line collapsing defects of 2-
dimensional randomtest pattern of a very low K1 process. The target is moved by minimizing the process
variation band and the pitches of hotspot points are relaxed.The image quality improvement is thenchecked.
Model driven target optimized NILS and MEEF at the weakest hotspot point are improved to 1.22 and 5.5
from the values 0.79 and 10.6 of a traditional OPCwith advanced solver, respectively. The pattern collapsing
hotspot is then validated to be repaired by optimizing target position. A full hotspot fixer flow including
model-driven target optimization using ILT can also be extended into DFM applications.
As the industry pushes to ever more complex illumination schemes to increase resolution for next generation memory
and logic circuits; subresolution assist feature (SRAF) placement requirements become increasingly severe. Therefore
device manufacturers are evaluating improvements in SRAF placement algorithms which do not sacrifice main feature
(MF) patterning capability. AF placement algorithms can be categorized broadly as either rule-based (RB), model-based
(MB). However, combining these different algorithms into new integrated solutions may enable a more optimal overall
RBAF is the baseline AF placement method for many previous technology nodes. Although RBAF algorithm
complexity limits its use with very extreme illumination, RBAF is still a powerful option in certain scenarios. One
example is for repeating patterns in memory arrays. RBAF algorithms can be finely optimized and verified
experimentally without the building of complex models. RBAF also guarantees AF placement consistency based only
on the very local geometric environment, which is important in applications where consistent signal propagation is of
MBAF algorithms deliver the ability to reliably place assist features for enhanced process window control across a wide
variety of layout feature configurations and aggressive illumination sources. These methods optimize sophisticated AF
placement to improve main feature PW but without performing full main feature OPC. The flexibility of MBAF allows
for efficient investigations of future technology nodes as the number of interactions between local layout features
increases beyond what RBAF algorithms can effectively support
Based on hybrid approach algorithms combining features of the different algorithms using both RBAF and MBAF
methods, the generation and placement of SRAF can be a good alternative. Combining of two kinds of SRAF placement
options might result in relatively improved process window compared to an independent approach since two methods
are capable of supplement each other with a complementary advantages.
In this paper we evaluate the impact of SRAF configuration to pattern profile as well as CD margin window and
manufacturing applications of MBAF and Hybrid approach algorithms compared to the current OPC without AF. As a
conclusion, we suggest methodology to set up optimum SRAF configuration using these AF methods with regard to
It is necessary to apply extreme illumination condition on real device as minimum feature size of the device
shrinks. As k1 decrease, ultra extreme illumination has to be used. However, in case of using this illumination, CD and
process windows dramatically fluctuate as pupil shapes slightly changes. For past several years, Pupil Fit Modeling
(PFM) was developed in order to analyze pupil shape parameters which are independent from each others. The first
object in this work is to distinguish pupil shape of different scanner by separating more parameters. According to pupil
parameter analysis, the major factors of CD or process window difference between two scanner systems obviously
appear. Due to correlation between pupil parameter and scanner knob, pupil parameter analysis would be clearly
identified which scanner knob should be compensated. The second object is to define specification of each parameter by
using analysis of CD budget for each pupil parameters. Using periodic monitoring of pupil parameter which is controlled
by previous specification, scanner system in product lines can be maintained at ideal state. Additionally, OPC model
accuracy enhancement should be obtained by using highly accurate fitted pupil model. Recently, other application of
pupil model is reported for improvement of OPC and model based verification model accuracy. Such as modeling using
average optics and hot spot detection of scanner specific model are easily adopted by using pupil fit model. Therefore,
applications of pupil fit parameter for process model are very useful for improvement of model accuracy.
In our study, the quantity of model accuracy enhancement using PFM is investigated and analyzed. OPC and
hotspot point detection capability results with pupil fit model would be shown. Also, in this paper, trends of CD and
process window for each scanner parameter are evaluated by using pupil fit model. As of results, we were able to find
which pupil parameter has influence in critical layer CD and application of this result resulted in better accuracy in
detecting hotspot for model based verification.
As K1 factor for mass-production of memory devices has been decreased to almost its theoretical limit, the process
window of lithography is getting much smaller and the production yield has become more sensitive to even small
variations of the process in lithography. So it is necessary to control the process variations more tightly than ever. In
mass-production, it is very hard to extend the production capacity if the tool-to-tool variation of scanners and/or scanner
stability through time is not minimized. One of the most critical sources of variation is the illumination pupil. So it is
critical to qualify the shape of pupils in scanners to control tool-to-tool variations.
Traditionally, the pupil shape has been analyzed by using classical pupil parameters to define pupil shape, but these
basic parameters, sometimes, cannot distinguish the tool-to-tool variations. It has been found that the pupil shape can be
changed by illumination misalignment or damages in optics and theses changes can have a great effect on critical
dimension (CD), pattern profile or OPC accuracy. These imaging effects are not captured by the basic pupil parameters.
The correlation between CD and pupil parameters will become even more difficult with the introduction of more
complex (freeform) illumination pupils.
In this paper, illumination pupils were analyzed using a more sophisticated parametric pupil description (Pupil Fit
Model, PFM). And the impact of pupil shape variations on CD for critical features is investigated. The tool-to-tool
mismatching in gate layer of 4X memory device was demonstrated for an example. Also, we interpreted which
parameter is most sensitive to CD for different applications. It was found that the more sophisticated parametric pupil
description is much better compared to the traditional way of pupil control. However, our examples also show that the
tool-to-tool pupil variation and pupil variation through time of a scanner can not be adequately monitored by pupil
parameters only, The best pupil control strategy is a combination of pupil parameters and simulated CD using measured
illumination pupils or modeled pupils.
The study of OPC (Optical Proximity Correction) model that well predict the wafer result has been
researched. As the pattern design shrink down, the need for the CD (Critical Dimension) controllability
increased more than before. To achieve these requirements, OPC models must be accurate for full chip
process and model inaccuracies are one of several factors which contribute to errors in the final wafer image.
For that reason, robust OPC using real lithographic terms was proposed. Real lithographic system is quite
different from ideal system that is used for OPC modeling. Until now, this difference was acceptable since
pattern size used for OPC model was large, but as device size shrinks, this gap between ideal and real system
causes degradation of OPC accuracy. So, various optical parameters such as apodization, laser band width,
degree of polarization, illumination are used today in order to compensate for this issue. Especially, major
issue in modeling error is related to how the illumination source is used. For this study we assess accuracy of optical model for robust OPC using ideal and actual illumination
sources, and test conditions are as follows: 1) We examined the difference of pupil types to output model respectively; 2) A parameterized test pattern layout was used by 1D test pattern types that have various lines and spaces; 3) All models were calculated in automation method so as to exclude the dependency of user skills; 4) OPC accuracies were examined by gate layer patterns on full chip level. The study is performed for 5X~4Xnm nodes lithographic processes. The main focus of the study was on usability of model that is made by measured source data in semiconductor manufacturing. Results clearly showed that the actual source for the optical model has merits and demerits.
As the design rule of device shrinks down, it is difficult to enlarge the process window, especially DOF (Depth of Focus). It has shown good results in resolution issues with short wavelength, high NA aperture and several RET (Resolution Enhancement Technique) like special illuminator and mask techniques and so on. But it needs to be challenged for DOF process window in contact / via process having various pitch and pattern location. It is a key point in sub 100nm process development and product. It is demonstrated that focus scan method is effective for DOF improvement in contact and via layers. Focus Scan method is one of the focus drilling techniques; it is realized to tilt wafer stage so that the same point on the wafer field can be exposed in limited continual focus range using multiple focal planes through the slit of scanner tool. In this study, confirmation was inspected for simulation and wafer evaluation for focus scan effects in view of process feasibility. DOF increased over 50% with focus scan in contact mask process even though there are several issues to be solved and considered. Energy Latitude (EL) decreased a little by image contrast drop, but if we consider the process window for evolution of device, it is relatively enough for process. OPC or Bias tuning is needed for application in contact layer having various pitch and location, and overlay issues are needed to confirm for each illuminator. From these experiments, it is found that DOF margin can easily be enhanced using focus scan method. Also some fine tuning is required to adequately use this method on production devices.