A two-step full-chip simulation method for optimization of sub-resolution assist feature placement in a random
logic Contact layer using ArF immersion Lithography is presented. Process window, characterized by depth of
focus (DOF) , of square or rectangular target features is subject to optimization using the optical and resist effects
described by calibrated models (Calibre ®
nmOPC, nmSRAF simulation platform). By variation of the assist
feature dimension and their distance to main feature in a test pattern, a set of comprehensive rules is derived
which is applied to generate raw assist features in a random logic layout. Concurrently with the generation of
the OPC shapes for the main features, the raw assist feature become modified to maximize process window and
to ensure non-printability of the assist features. In this paper, the selection of a test pattern, the generation of
a set of "golden" rules of the raw assist feature generation and their implementation as well as the assist feature
coverage in a random logic layout is presented and discussed with respect to performance.
As semiconductor technologies move toward 70nm
generation and below, contact-hole is one of the most
challenging features to print on wafer. There are two
principle difficulties in defining small contact-hole
patterns on wafer. One is insufficient process margin
besides poor resolution compared with line-space pattern.
The other is that contact-hole should be made through
pitches and random contact-hole pattern should be
fabricated from time to time.
PIXBAR technology is the candidate which can help
improve the process margin for random contact-holes.
The PIXBAR technology lithography attempts to
synthesize the input mask which leads to the desired
output wafer pattern by inverting the forward model from
mask to wafer. This paper will use the pixel-based mask
representation, a continuous function formulation, and
gradient-based interactive optimization techniques to
solve the problem. The result of PIXBAR method helps
gain improvement in process window with a short
learning cycle in contact-hole pattern assist-feature
In state of the art integrated circuit industry for transistors gate length of 45nm and beyond, the sharp distinction between
design and fabrication phases is becoming inadequate for fast product development. Lithographical information along
with design rules has to be passed from foundries to designers, as these effects have to be taken into consideration during
the design stage to insure a Lithographically Friendly Design, which in turn demands new communication channels
between designers and foundries to provide the needed litho information. In the case of fabless design houses this
requirement is faced with some problems like incompatible EDA platforms at both ends, and confidential information
that can not be revealed by the foundry back to the design house.
In this paper we propose a framework in which we will try to demonstrate a systematic approach to match any
lithographical OPC solution from different EDA vendors into CalibreTM. The goal is to export how the design will look
on wafer from the foundry to the designers without saying how, or requiring installation of same EDA tools.
In the developed framework, we will demonstrate the flow used to match all steps used in developing OPC starting from
the lithography modeling and going through the OPC recipe. This is done by the use of automated scripts that
characterizes the existing OPC foundry solution, and identifies compatible counter parts in the CalibreTM domain to
generate an encrypted package that can be used at the designers' side.
Finally the framework will be verified using a developed test case.
Scatter Bar (SBAR) insertion is a computationally expensive operation. SBAR are usually generated rule-based. SBAR rule tables dictate the insertion of SBAR with different SBAR width dependent on the width of the printable main features and the spacing between the main features and SBAR. Optimization of the SBAR rules drives manufactures to ever more complex SBAR tables which increase the runtime. In advanced process nodes, SBAR printing issues, missing SBAR due to clean-up problems and joining SBAR of different width together remain challenging. On the other hand, pixelized inversion methods may yield optimized SBAR solutions, especially in terms of SBAR placement for contact layers, but comes at the expense of significant computational effort and increased mask writing and inspection time. Since OPC changes the spacing between SBAR and main features, an accurate and optimized SBAR solution requires OPC and SBAR optimization to run interactively.
This work focuses on both line/space and contact layers To ensure fast SBAR optimization, SBAR placement and SBAR width optimization are separated. SBAR of uniform width are placed fast driven by a simple rule-based table comprising only a single SBAR width. This intermediate SBAR layer is subject into a model-based approach, which fragments the SBAR layer based on proximity with respect to the main features or other SBAR, and assigns measurement sites to each SBAR fragment. A model is used to move each SBAR fragment inward or outward so that the image cut line shows a maximum SBAR intensity closer to a predefined SBAR printing threshold. While the main features are unchanged, several iterations are applied to converge the SBAR fragments. Keeping the SBAR fragments fixed, OPC is applied to the main features. Repeating these steps allows optimization of the SBAR width and the OPC simultaneously. Site based as well as contours based verification methods are applied to ensure that the SBAR printing margin has been significantly improved. The improved SBAR printing margin allows manufactures to apply more aggressive SBAR placement rules, which, in addition to the optimized SBAR width, helps to enlarge the depth of focus, therefore, widen the common process window of the lithography process.
Model-based optical proximity correction (OPC) is an indispensable production tool enabling successful extension of
photolithography down to sub-80nm regime. Commercial OPC software has established clear procedures to produce
accurate OPC models at best focus condition. However, OPC models calibrated at best focus condition sometimes fail to
prevent catastrophic circuit failure due to patterning short & open caused by accidental shifts of dose/ focus within the
corners of allowed processes window.
A novel model-based OPC verification methodology is presented in this work, which precisely pinpoints post OPC
photolithography failures in VLSI circuits through the entire lithographic process window. By application of a critical
photolithography process window model in OPC verification software, we successfully uncovered all weak points of a
design prior tape out, eliminating high risk of circuits open & shorts at the extreme corner of the lithographic process
window in any complex circuit layout environment. The process window-related information is usually not taken into
consideration when running OPC verification procedures with models calibrated at nominal process condition.
Intensive review of the critical dimension (CD) and top-view SEM micrographs from the weak points indicate matching
between post OPC simulation and measurements. Using a single highly accurate process window resist model provides a
reliable OPC verification methodology when used in a field- or grid-based simulation engine ensuring manufacturability
within the largest possible process window for any modern critical design.