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While the EPE from variation in aberrations across the exposure field is correctable in OPC software, there are no known ways to address tool-to-tool aberration variation. Given that foundries are expected to have multiple EUV tools for high volume manufacturing, the degree of tool-matching between different machines is expected to play a critical role to the success of EUV. This work seeks to further the study by quantifying the simulated edge placement error on realistic 7 nm / 5 nm node designs resulting from a fleet consisting of multiple EUV tools, under the assumption of single OPC model / mask for multiple tools and whether such assumptions are valid. Given the importance of tool-to-tool aberration matching in EUVL, this study investigates the amount of variation in tool-to-tool aberration that can be tolerated before foundries must consider tool dedicated OPC mask sets. This study statistically analyzes different metrics such as EPEs, image shifts and worst case excursions to understand which single tool in the fleet should be best used in model calibration to generate the OPC mask shapes. In addition, an effort to rank relative quality of the verification solutions is investigated, to be used to tool allocation.
We will demonstrate verification flows for different process modules to verify the failure mechanisms and to aid in visualization, then judge the areas for improvement with existing model based solutions. Then we will also try to investigate possible area for development of accurate residual error prediction from compact models as those errors are accumulated from multiple process effects into final CD measurement from design target layers. This may lead to new dimensions of modeling process effects we’ve never considered because those signatures were lumped between processes to processes.
In-line CD and overlay metrology specifications are typically established by starting with design rules and making certain assumptions about error distributions which might be encountered in manufacturing. Lot disposition criteria in photo metrology (rework or pass to etch) are set assuming worst case assumptions for CD and overlay respectively. For example poly to active overlay specs start with poly endcap design rules and make assumptions about active and poly lot average and across lot CDs, and incorporate general knowledge about poly line end rounding to ensure that leakage current is maintained within specification. This worst case guard banding does not consider specific chip designs, however and as we have previously shown full-chip simulation can elucidate the most critical "hot spots" for interlayer process variability comprehending the two-layer CD and misalignment process window. It was shown that there can be differences in X versus Y misalignment process windows as well as positive versus negative directional misalignment process windows and that such design specific information might be leveraged for manufacturing disposition and control schemes.
This paper will further investigate examples of via-metal model-based analysis of CD and overlay errors. We will investigate both single patterning and double patterning. For single patterning, we show the advantage of contour to contour simulation over contour to target simulation, and how the addition of aberrations in the optical models can provide a more realistic PW window for edge placement errors. For double patterning, the interaction of 4 layer CD and misalignment errors is very complex, but we illustrate that not only can full-chip verification identify potential rEPE hotspots, the OPC engine can act to mitigate such hotspots and enlarge the overall combined CD-overlay rEPE process window.
This will count as one of your downloads.
You will have access to both the presentation and article (if available).
The microlithography process is critical to the successful manufacture of integrated circuits. Control of the critical dimension (CD) of the device is paramount to producing devices that meet design specification.
Eight critical process categories that control feature size are considered. This course looks at each category and discusses the impact that parameter variation has on the lithography process, on device yield and on final device performance. Emphasis is placed on the chemical and physical relationships within the lithography process.This course will consider lithography methods and process tuning appropriate for production lithography now that production is moving below historical limits.This is an excellent opportunity to get advice and specific direction on resist processing.
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