Dr. John L. Sturtevant
Director of Product Development at Siemens EDA
SPIE Involvement:
Author | Editor | Instructor
Publications (92)

Proceedings Article | 23 March 2020 Presentation + Paper
Proc. SPIE. 11323, Extreme Ultraviolet (EUV) Lithography XI
KEYWORDS: Stochastic processes, Extreme ultraviolet lithography, Photons, Photoresist processing, Failure analysis, Extreme ultraviolet, Calibration, Statistical analysis, Data modeling, Semiconducting wafers

Proceedings Article | 20 March 2020 Presentation + Paper
Proc. SPIE. 11325, Metrology, Inspection, and Process Control for Microlithography XXXIV
KEYWORDS: Stochastic processes, SRAF, Failure analysis, Printing, Extreme ultraviolet, Line edge roughness, Photoresist materials, Semiconducting wafers, Extreme ultraviolet lithography, Photons

Proceedings Article | 20 March 2020 Presentation + Paper
Proc. SPIE. 11325, Metrology, Inspection, and Process Control for Microlithography XXXIV
KEYWORDS: Semiconducting wafers, Data modeling, Overlay metrology, Metals, Metrology, Critical dimension metrology, Databases, Inspection, Computer simulations, Scanners

Proceedings Article | 20 March 2019 Presentation + Paper
Proc. SPIE. 10962, Design-Process-Technology Co-optimization for Manufacturability XIII
KEYWORDS: Failure analysis, Critical dimension metrology, Lithography, Logic, Manufacturing, Photomasks, Error analysis, Stochastic processes, Visualization, Optical proximity correction

Proceedings Article | 2 January 2019 Presentation + Paper
Proc. SPIE. 10809, International Conference on Extreme Ultraviolet Lithography 2018
KEYWORDS: Photomasks, Extreme ultraviolet, Source mask optimization, Resolution enhancement technologies, Tantalum, SRAF, Lithography, Logic, Image enhancement, Image processing

Showing 5 of 92 publications
Proceedings Volume Editor (7)

Showing 5 of 7 publications
Conference Committee Involvement (18)
Design-Process-Technology Co-optimization for Manufacturability XII
28 February 2018 | San Jose, California, United States
Design-Process-Technology Co-optimization for Manufacturability XI
1 March 2017 | San Jose, California, United States
Design-Process-Technology Co-optimization for Manufacturability X
24 February 2016 | San Jose, California, United States
Design-Process-Technology Co-optimization for Manufacturability IX
25 February 2015 | San Jose, California, United States
Design-Process-Technology Co-optimization for Manufacturability VIII
26 February 2014 | San Jose, California, United States
Showing 5 of 18 Conference Committees
Course Instructor
SC121: Practical Process Design for Microlithography
The microlithography process is critical to the successful manufacture of integrated circuits. Control of the critical dimension (CD) of the device is paramount to producing devices that meet design specification. Eight critical process categories that control feature size are considered. This course looks at each category and discusses the impact that parameter variation has on the lithography process, on device yield and on final device performance. Emphasis is placed on the chemical and physical relationships within the lithography process.This course will consider lithography methods and process tuning appropriate for production lithography now that production is moving below historical limits.This is an excellent opportunity to get advice and specific direction on resist processing.
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