As patterns shrink to physical limits, advanced Resolution Enhancement Technologies (RET) encounter increasing challenges to ensure a manufacturable Process Window (PW). Moreover, due to the wide variety of pattern constructs for logic device layers, lithographically weak patterns (spots) become a difficult obstacle despite Source and Mask co- Optimization (SMO) and advanced OPC being applied. In order to overcome these design related lithographically weak spots, designers need lithography based simulator feedback to develop robust design rules and RET/OPC engineers must co-optimize the overall imaging capability and corresponding design lithography target. To meet these needs, a new optimization method called SmartDRO (Design Rule Optimization) has been developed. SmartDRO utilizes SMO’s Continuous Transmission Mask (CTM) methodology and optimization algorithm including design target variables in the cost function. This optimizer finds the recommended lithography based target using the SMO engine. In this paper, we introduce a new optimization flow incorporating this SmartDRO capability to optimize the target layout within the cell to improve the manufacturable process window. With this new methodology, the most advanced L/S patterns such as metal (k1 = 0.28) and the most challenging contact patterns such as via (k1 = 0.33) are enabled and meet process window requirements.
An illuminator and mask patterns were optimized (SMO) to minimize CD variation of a set of contact patterns selected
from logic layouts and an array of SRAM cells. MEEF and defocus characteristics of the target patterns were modeled as
functions of constraints on minimum mask features and spaces (MRC). This process was then repeated after linearly
shrinking the input patterns by 10%. Common statistical measures of CD control worsen as MRC becomes more
restrictive, but these are weak indicators compared to behavior at points in the image that exhibit high MEEF or low
depth of focus. SMO solutions for minimum MEEF and maximum depth of focus are different, so some compromise is
necessary. By including exposure time among the variables to be optimized, some control over local mask bias is made
available to minimize MEEF and loss of litho quality due to MRC.
In microelectronics manufacturing, photolithography is the art of transferring pattern shapes printed on a mask to silicon
wafers by the use of special imaging systems. These imaging systems stopped reducing exposure wavelength at 193nm.
However, the industry demand for tighter design shapes and smaller structures on wafer has not stopped. To overcome
some of the restrictions associated with the photographic process, new methods for Resolution Enhancement Techniques
(RET) are being constantly explored and applied. An essential step in any RET method is Optical Proximity Correction
(OPC). In this process the edges of the target desired shapes are manipulated to compensate for light diffraction effects
and result in shapes on wafer as close as possible to the desired shapes. Manipulation of the shapes is always restricted
by Mask Rules Checks (MRCs). The MRCs are the rules that assure that the pattern coming out of OPC can be printed
on the mask without any catastrophic faults. Essential as they are, MRCs also place constrains on the solutions explored
by the OPC algorithms.
In this paper, an automated algorithm has been implemented to overcome MRC limitations to RET by decomposing the
original layout at the places where regular RET hit the MRC during OPC.This algorithm has been applied to test cases
where simulation results showed much better printability than the normal conventional solutions. This solution has also
been tested and verified on silicon.
As integrated circuit technology advances and features shrink, the scale of critical dimension (CD) variations induced by
lithography effects become comparable with the critical dimension of the design itself. At the same time, each
technology node requires tighter margins for errors introduced in the lithography process. Optical and process models --
the black boxes that simulate the pattern transfer onto silicon -- are becoming more and more concerned with those
different process errors. As a consequence, an optical proximity correction (OPC) model consists mainly of two parts; a
physical part dealing with the physics of light and its behavior through the lithographical patterning process, and an
empirical part to account for any process errors that might be introduced between writing the mask and sampling
measurements of patterns on wafer. Understanding how such errors can affect a model's stability and predictability, and
taking such errors into consideration while building a model, could actually help convergence, stability, and
predictability of the model when it comes to design patterns other than those used during model calibration and
verification. This paper explores one method to quickly enhance model accuracy and stability.
As devices size move toward 90nm technology node or below, defining uniform bit line CD of flash devices is one of
the most challenging features to print in KrF lithography. There are two principal difficulties in defining bit line on wafer.
One is insufficient process margin besides poor resolution compared with ArF lithography. The other is that asymmetric
bit line should be made for OPC(Optical Proximity Correction) modeling. Therefore advanced ArF lithography scanner
should be used for define bit line with RETs (Resolution Enhancement Techniques) such as immersion lithography, OPC,
PSM(Phase Shift Mask), high NA(Numerical Aperture), OAI(Off-Axis Illumination), SRAF(Sub-resolution Assistant
Feature), and mask biasing.. Like this, ArF lithography propose the method of enhancing resolution, however, we must
spend an enormous amount of CoC(cost of ownership) to utilize ArF photolithography process than KrF.
In this paper, we suggest method to improve of bit line CD uniformity, patterned by KrF lithographic process in 90nm
sFlash(stand alone Flash) devices. We applied new scheme of mask manufacturing, which is able to realize 2 different
types of mask, binary and phase-shift, into one plate. Finally, we could get the more uniform bit lines and we expect to
get more stable properties then before applying this technique.
Flare has become a significant problem for low K1 lithography process. It is generally divided into three parts:
long-, local-, short-range. Long-range flare is scattering over a scale of tens of microns, come from reflections within the
projection lens. Short-range is scattering over a scale of about 1 micron or less, come from lens aberrations. And localrange
flare is scattering over about 1 to 10 microns, comes from inhomogenieties within glass and local pattern density.
Especially, local-range flare causes the printed width to vary or degrade printing accuracy. Normally, the local-range
flare effect is increase by local pattern density. Therefore the local flare effect can be reduced if the effect of local pattern
density within die is compensated effectively.
In this paper, we discussed full chip compensation for local flare effect using OPC/DRC method. First of all, we
investigated relationship between local flare and pattern density using test pattern and extracted OPC model according
to pattern density and also analyzed within chip pattern density distribution using DRC. We separated original layout to
OPC target layout according to local pattern density, applied different OPC model to each separated layout. We will
show within chip CD variation was improved after local flare effects reduction.
Resolution enhancement technologies (RET), such as optical proximity correction (OPC) help us develop sub-
100nm technology node by using photolithography equipments and materials for 130nm photolithographic process.
Because the resolution of scanner and materials has arrived almost at their limit, small patterns below resolution limit are
more sensitively affected by very small tolerance of various factors which were not considered by major process
parameters such like lens flare, reticle haze, reticle critical dimensional (CD) errors, etc. As patterning small ones under
resolution limit directly means large MEEF (mask error enhancement factor) in photo process, reticle CD errors are
actually magnified on wafer. Therefore, reticle CD errors should be tightly controlled when we try to define small
patterns under resolution limit.
As the feature size shrinks down, the importance of OPC model accuracy grows up for the purpose of ensuring
high pattern fidelity. In conventional process of OPC model generation, we don't concern how mask database CDs are
exactly matched with real reticle CDs, since the specification of reticle CD is enough tight to ignore CD variation on the
reticle such as 1-dimensional CD difference, linearity CD uniformity. But in the process with large MEEF, OPC model
with incorrect CD information of reticle has a bad influence to prediction pattern fidelity.
In this paper, we describe the effect of reticle CD errors on the OPC model accuracy. To quantify that effect, we
compared two cases of OPC model generation. One is making OPC model by using mask database CDs themselves, the
other is by using mask real CDs in 110nm node for poly and metal 1 (damascene) layers. As a consequence of the test,
we can achieve the accuracy OPC model calibrated with reticle CD errors which better predicts wafer CDs and 2-
dimensional images than the model, calibrated by original database CDs.
Flare is unwanted light arriving at the wafer and light causing negative impact on pattern formation. It is caused
by scattered light from lens surfaces, problem on lens design, or problem on lens manufacture. The impact of flare varies
printed line widths or drops CD uniformity accuracy in full chip. And, It is an added incoherent background intensity that
will degrade OPC(Optical Proximity Correction) accuracy.
In this paper, we discussed CD variation, MEEF (Mask Error Enhancement Factor) and OPC accuracy by the
flare effects. Flare is bound up with local pattern density. Local pattern density influences background intensity by flare
or stray light. So we studied CD variation, MEEF, OPC modeling data with local pattern density by several experiment.
Also, in this study, we will discuss test pattern drawing for OPC modeling data, analyze CD difference between OPC test
pattern with considering flare effect and test pattern with regardless flare effect and MEEF value by flare effect. MEEF is
main factor that influences lithography process margin. This paper will show test pattern optimization in OPC modeling.
Deep-UV (DUV) lithography has been developed to define minimum feature sizes of sub-100 nm dimensions of devices
semiconductor. In response to this trend, DUV mask technology has been proposed as an effective technique for
considering the reduction of mask making cost, especially, in low volume designs. However, the requirement of tight CD
control of the mask features in advanced devices is resulted in increasing of mask cost. In this research, we discussed
two different typed image tones comparison, positive and negative tone, in DUV lithography. The choice of final mask
tone needs to be selected as function of pattern density and shape. The evaluation items to judge if the mask is good are
the OPC model accuracy, resolution and mask throughput. Both mask process and manufacturing throughput are affected
by image tone type of positive and negative. This paper will show the procedures and results of experiment.