The insertion of SRAF(Sub-Resolution Assist Feature) is one of the most frequently used method to enlarge the process window area. In most cases, the size of SRAF is proportional to the focus margin of drawn patterns. However, there is a trade-off between the SRAF size and SRAF printing, because SRAF is not supposed to be patterned on a wafer. For this reason, a lot of OPC engineers have been tried to put bigger and more SRAFs within the limits of the possible. The fact that many papers about predicting SRAF printability have been published recent years reflects this circumstance. Pattern dummy is inserted to enhance the lithographic process margin and CD uniformity unlike CMP dummy for uniform metal line height. It is ordinary to put pattern dummy at the designated location under consideration of the pitch of real patterns at design step. However, it is not always desirable to generate pattern dummies based on rules at the lithographic point of view. In this paper, we introduce the model based pattern dummy insertion method, which is putting pattern dummies at the location that model based SRAF is located. We applied the model based pattern dummy to the layers in logic devices, and studied which layer is more efficient for the insertion of dummies.
It is a distinctive feature of the metal contact layout in NAND flash memory devices that there are small-pitch contact patterns and random-pitch contact patterns in one layout. This kind of pitch difference between cell array patterns and isolated single patterns hadn’t had a decisive effect on wafers when the illumination condition is not aggressive. However, the pattern pitch difference has caused various problems including the best focus shift due to extreme illuminations. The common DOF margin of a contact layout is degraded when the best focus depth for each pattern is variable. Mask topography effect is well known for the major cause of best focus shift between contact patterns which have different pitches. The demand for device technology node shrink for production cost reduction has required adoption of hyper NA illumination conditions, and this aggressive illumination made it hard to secure an enough common DOF margin due to the best focus shift. In this work, the best focus shift phenomenon among different-pitch patterns caused by mask 3D effects is studied according to the various illumination conditions. It is found that the more aggressive illumination condition is and the bigger the pitch difference among patterns in one layout is, the bigger the best focus shift become. Also, we suggest the solution for avoiding this DOF margin degradation, which is SRAF optimization.
Scanner mismatch has become one of the critical issues in high volume memory production. There are several
components that contribute to the scanner CD mismatch. One of the major components is illumination pupil difference
between scanners. Because of acceleration of dimensional shrinking in memory devices, the CD mismatch became more
critical in electrical performance and process window.
In this work, we demonstrated computational lithography model based scanner matching for sub 3x nm memory devices.
We used ASML XT:1900Gi as a reference scanner and ASML NXT:1950i as the to-be-matched scanner. Wafer
metrology data and scanner specific parameters are used to build a computational model, and determine the optimal
settings by model simulation to minimize the CD difference between scanners. Nano Geometry Research (NGR) was
used as a wafer CD metrology tool for both model calibration and matching result verification. The extracted pupil
parameters from measured source map from both before and after matching are inspected and analyzed. Simulated and
measured process window changes by applying the matching sub-recipe are also evaluated.
It is necessary to apply extreme illumination condition on real device as minimum feature size of the device
shrinks. As k1 decrease, ultra extreme illumination has to be used. However, in case of using this illumination, CD and
process windows dramatically fluctuate as pupil shapes slightly changes. For past several years, Pupil Fit Modeling
(PFM) was developed in order to analyze pupil shape parameters which are independent from each others. The first
object in this work is to distinguish pupil shape of different scanner by separating more parameters. According to pupil
parameter analysis, the major factors of CD or process window difference between two scanner systems obviously
appear. Due to correlation between pupil parameter and scanner knob, pupil parameter analysis would be clearly
identified which scanner knob should be compensated. The second object is to define specification of each parameter by
using analysis of CD budget for each pupil parameters. Using periodic monitoring of pupil parameter which is controlled
by previous specification, scanner system in product lines can be maintained at ideal state. Additionally, OPC model
accuracy enhancement should be obtained by using highly accurate fitted pupil model. Recently, other application of
pupil model is reported for improvement of OPC and model based verification model accuracy. Such as modeling using
average optics and hot spot detection of scanner specific model are easily adopted by using pupil fit model. Therefore,
applications of pupil fit parameter for process model are very useful for improvement of model accuracy.
In our study, the quantity of model accuracy enhancement using PFM is investigated and analyzed. OPC and
hotspot point detection capability results with pupil fit model would be shown. Also, in this paper, trends of CD and
process window for each scanner parameter are evaluated by using pupil fit model. As of results, we were able to find
which pupil parameter has influence in critical layer CD and application of this result resulted in better accuracy in
detecting hotspot for model based verification.
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