Experimental local CD uniformity (LCDU) of the dense contact-hole (CH) array pattern is statistically decomposed into stochastic noise, mask component, and metrology factor. Each component are compared quantitatively, and traced after etching to find how much improvement can be achieved by smoothing. Etch CDU gain factor is defined as the differential of etch CD by resist CD, and used to estimate etch CDU on resist CDU. Stochastic noise has influenced on not only LCDU but also local placement error (LPE) of each contact-hole. This LPE is also decomposed into its constituents in the same statistical way. As a result, stochastic noise is found to be the most dominant factor on LCDU and LPE. Etch LCDU is well expected by Etch Gain factor, but LPE seems to be kept same after etching. Fingerprints are derived from the repeating component and the boundary size for excluding proximity effect in analysis is investigated.
Intra-field CD uniformity control is one of hurdles in EUV lithography. Reflection imaging system intrinsic to EUV
causes CD non-uniformity especially in exposure field edge. To analyze dominant contributors to make this intra-field
CD non-uniformity in EUV lithography, influence of flare from adjacent fields and in-band and out of band refection
from reticle masking blind(REMA) and mask black border were investigated through intensive sampling of CD
measurement. Also mask border condition and REMA open settings are split into various settings to find out the impacts
from each contributor. Two ASML EUV scanners, alpha demo tool(ADT) and pre-production tool(PPT) are used for the
experiment. Fortunately, DUV out of band(OoB), reflection of REMA and the flare from adjacent fields are found to be
not significant in NXE3100. The results presented here lead us to the conclusion that the EUV refection from mask black
border is the main contributor and CD non-uniformity of the field edge can be overcome through optimized REMA
Extreme ultraviolet lithography is about to be realized in mass production even though there are many obstacles to be
overcome. Several years ago, the EUV pellicle was suggested by some people, but the idea of using the EUV pellicle
was abandoned by most people because there were big problems that were believed to be almost impossible to
overcome. The EUV pellicle should be made of an inorganic material instead of a common organic pellicle and should
be very thin due to EUV transmission. In addition to that the support of the very thin pellicle film should be used. The
structure of the support of the pellicle thin film should not make any noticeable intensity difference on the top of the
patterned mask side. However, the experimental result of the Intel showed the interference images with their suggested
support structure. In the Intel's report, the structure of the support was honeycomb or regular mesh type with a ~ 10 μm
line width and a ~100 μm pitch size. We study the intensity distributions on the top of mask for various combinations
around the above the mentioned scales and the support structures. The usable structure of the support will be reported
based on our simulation results, which would open the possibility of the EUV pellicle in mass production.
Extreme Ultra-Violet (EUV) lithography is almost only solution reachable for next-generation lithography below 30nm
half pitch with relative cost competitiveness. In this study, we investigate the feasibility of EUV lithography for applying
2X nm dynamic random access memory (DRAM) patterning. Very short wavelength of 13.5nm adds much more
complexity to the lithography process. To understand for challenges of EUV lithography for high volume manufacturing
(HVM), we study some EUV specific issues by using EUV full-field scanners, alpha demo tool (ADT) at IMEC and pre-production
tool (PPT) at ASML. Good pattern fidelity of 2X nm node DRAM has been achieved by EUV ADT, such as
dense line and dense contact-hole. In this paper, we report on EUV PPT performance such as resolution limit, MEEF,
across slit CD uniformity (CDU) and focus & exposure latitude margin with 2X nm node DRAM layers in comparison
with ADT performance. Due to less flare and aberration of PPT, we have expected that PPT shows good performance.
EUV lithography is the leading candidate for sub-32nm half-pitch device manufacturing. EUV Pre-Production Tool
(PPT) is expected to be available at the end of 2010. As EUVL era comes closer, EUVL infrastructure has to get mature
including EUVL mask stack. To reduce HV CD bias which comes from shadowing effect, thin mask stack has been
considered. We presented that EUVL mask with 58nm absorber height shows same printing performance with
conventional EUVL mask with 80nm absorber height in our previous work. CD change and pattern damage at the
exposure field edges due to light leakage from the neighboring fields were also demonstrated.
In this paper, optimal mask stack which shows lower H-V CD bias than conventional structure using 70-nm-thick
absorber is proposed. To find minimized absorber height for sub-32nm pattering experimentally, printing result of
conventional mask and thin mask stack with 1:1 L/S patterns will be compared. Further-on, we demonstrate the printing
result of the reticle which is designed to minimize CD error at the exposure field edges due to mask black border
reflectivity by reducing reflectivity from the absorber.
All the wafers are exposed at ASML Alpha Demo Tool (ADT) and Pre-Production Tool (PPT) S-litho EUV is used for
Flare is hard to control only by hardware-wise means in EUV lithography. Therefore flare compensation through layout
correction is necessary. PSF is measured along various slit positions by using clearing resist pad with various sizes in
EUV Alpha Demo Tool (ADT) in IMEC. The measured PSF is compared to that derived from mathematically calculated
PSD modeling from surface roughness of the projection optics by suppliers. Degree of variation in flare level of real
device is measured experimentally with real device layout with clearing pads in it.
Flare is calculated as convolution of PSF (Point Spread Function) and pattern density. This requires astronomical amount
of computational time, because PSF in EUV has a very long tail that could even reach around several tens of thousands micron range. Therefore we investigated the pattern density of real devices with increasing radius of annulus. If the pattern densities in each annulus are saturated in some level, convolution integral with shorter range is sufficient and longer tail part of PSF can be approximated with fixed DC flare level dependent on saturated pattern density. Finally we discuss about the pending issues regarding flare correction for real devices application of EUV lithography.
Conventional EVUL mask has 80nm absorber height which brings considerable shadowing effect. H-V CD bias of 40nm
line and space by shadowing effect is more than 4nm, and that is expected to increase much more for narrower patterns
by simulation. However various reports have been presented on mask shadowing bias correction, experimental results
are not reliable to derive required mask bias correctly. Even more difficulty will arise when complex 2D structures are
taken into account. Therefore minimization of shadowing effect by reducing absorber thickness is desirable. To transfer
EUV lithography from experimental stage to HVM era, we need to find optimum absorber height of EUVL mask which
allows us less shadowing effect with minimum loss of process window.
In this paper, we present optimal absorber height of EUV mask which has been found in terms of shadowing effect and
process window by simulation and exposure. To find minimized absorber height experimentally, we will compare the
printing result of conventional and thin mask stack using simple 1:1 line and space and island patterns. Simulated H-V
CD bias and process window will be presented.
In this paper, we will present applications of MoSi-based binary intensity mask for sub-40nm DRAM with hyper-NA
immersion scanner which has been the main stream of DRAM lithography. Some technical issues will be reported for
polarized illumination and mask materials in hyper-NA imaging. One att.PSM (Phase Shift Mask) and three types of
binary intensity mask are used for this experiment; those are ArF att.PSM ( MoSi:760Å , transmittance 6% ),
conventional Cr ( 1030Å ) BIM (Binary Intensity Mask), MoSi-based BIM ( MoSi:590Å , transmittance 0.1%) and multi
layer ( Cr:740Å / MoSi:930Å ) BIM. Simulation and experiment with 1.35NA immersion scanner are performed to study
influence of mask structure, process margin and effect of polarization. Two types of DRAM cell patterns are studied; one
is a line and space pattern and the other is a contact hole pattern through mask structure. Various line and space pattern is
also through 38nm to 50nm half pitch studied for this experiment. Lithography simulation is done by in-house tool based
on diffused aerial image model. EM-SUITE is also used in order to study the influence of mask structure and
polarization effect through rigorous EMF simulation. Transmission and polarization effects of zero and the first
diffraction orders are simulated for both att.PSM and BIM. First and zero diffraction order polarization are shown to be
influenced by the structure of masking film. As pattern size on mask decreases to the level of exposure wavelength,
incident light will interact with mask pattern, thereby transmittance changes for mask structure. Optimum mask bias is
one of the important factors for lithographic performance. In the case of att.PSM, negative bias shows higher image
contrast than positive one, but in the case of binary intensity mask, positive bias shows better performance than negative
one. This is caused by balance of amplitude between first diffraction order and zero diffraction order light.1
Process windows and mask error enhancement factors are measured with respect to several types of mask structure. In
the case of one dimensional line and space pattern, MoSi-based BIM and conventional Cr BIM show the best
performance through various pitches. But in the case of hole DRAM cell pattern, it is difficult to find out the advantage
of BIM except of exposure energy difference. Finally, it was observed that MoSi-based binary intensity mask for sub-
40nm DRAM has advantage for one dimensional line and space pattern.
In this paper, we will present comparison of DRAM cell patterning between ArF immersion and EUV lithography which
will be the main stream of DRAM lithography. Assuming that the limit of ArF immersion single patterning is around
40nm half pitch, EUV technology is positioned on essential stage because development stage of device manufacturer is
going down sub-40nm technology node. Currently lithography technology, in order to improve the limitation of ArF
immersion lithography, double patterning technology (DPT) and spacer patterning technology (SPT) have been
examined intensively. However, double patterning and spacer patterning technology are not cost-effective process
because of complexity of lithography process such as many hard mask stacks and iterative litho, etch process. Therefore,
lithography community is looking forward to improving maturity of EUVL technology.
In order to overcome several issues on EUV technology, many studies are needed for device application. EUV
technology is different characteristics with conventional optical lithography which are non-telecentricity and mask
topography effect on printing performance. The printed feature of EUV is shifted and biased on the wafer because of
oblique illumination of the mask. Consequently, target CD and pattern position are changed in accordance with pattern
direction, pattern type and slit position of target pattern.1
For this study, we make sub-40nm DRAM mask for ArF immersion and EUV lithography. ArF attenuated PSM (Phase
Shift Mask) and EUV mask (LTEM) are used for this experiment; those are made and developed by in-house captive
maskshop. Simulation and experiment with 1.35NA ArF immersion scanner and 0.25NA EUV full field scanner are
performed to characterize EUV lithography and to compare process margin of each DRAM cell. Two types of DRAM
cell patterns are studied; one is an isolation pattern with a brick wall shape and another is a storage node pattern with
contact hole shape. Line and space pattern is also studied through 24nm to 50nm half pitch for this experiment.
Lithography simulation is done by in-house tool based on diffused aerial image model. EM-SUITE and Solid-EUV are
also used in order to study characteristics of EUV patterning through rigorous EMF simulation. We also investigated
shadowing effect according to pattern shape and design rule respectively. We find that vertical to horizontal bias is
around 2nm on 32nm to 40nm half pitch line and space pattern. In the case of DRAM cell, we also find same result with
line and space pattern. In view of mask-making consideration, we optimize absorber etch process. So we acquire vertical
absorber profile and mask MTT(Mean To Target) within 10% of target CD through several pitch.
Process windows and mask error enhancement factors are measured with respect to several DRAM cell pattern. In the
case of one dimensional line and space and two dimensional brick wall pattern, vertical pattern shows the best
performance through various pitches because of lower shadowing effect than horizontal pattern. But in case of contact hole DRAM cell pattern such as storage node pattern, it has bigger MEF value than one or two dimensional pattern
because of independency of shadowing effect. Finally, we compare with 2x, 3x and 4x DRAM cell patterning
performance in terms of pattern fidelity, slit CD uniformity and shadowing effect.
In the field of lithography technology, EUV lithography can be a leading candidate for sub-30 nm technology node.
EUVL expose system has different characteristics compared to DUV exposure system. EUV source wavelength is short
and no material is transparent to the source. So off-axis reflective optic system is used for patterning in place of on-axis
refractive system of DUV system. And different reticle design is needed that consists of 40 pair of Mo/Si multi layer
and absorber layer in place of conventional mask. Because of the oblique incidence on the mask, shadowing effect is
occurred such as pattern asymmetry, shift and pattern bias depending on pattern orientation. For non-telecentric
characteristics of EUV scanner, shadowing effect produces CD variation versus field position. Besides, it is well
known that EUV scanner has bigger flare than conventional DUV scanner. Therefore, the correction of mask shadowing
effect and flare level are one of the important issues for EUV lithography.
In this paper, process window and MEF of EUV lithography has been examined by 3D mask simulation. CD
variation by shadowing is simulated for various pattern orientations. A shadowing correction method has been
calculated due to field position to reduce shadowing effect. And the correction effect is examined by simulation and
Experimental results. Principle of radial overlay shift due to field position is verified then the shift length of line and
space pattern is calculated.
In recent years, DRAM and Flash technology node has shrunk below to 45nm half pitch (HP) patterning with significant progresses of hyper numerical aperture (NA) immersion lithography system and process development. Several technologies such as extreme ultra violet (EUV) lithography, double patterning technology (DPT) and spacer patterning technology (SPT) have been developed for sub 40nm HP device. High index immersion lithography (HIL) is also one of the candidates for next generation lithography technology that has benefits of product cost, process simplification and usage for existing infrastructure though this technology must overcome critical issues--high index immersion fluid and lens optic development.
In this paper, we will present simulation results on sub 40nm imaging characterization for HIL.
First, we have studied the image performance for sub 40nm patterning with HIL. The image contrast, optical proximity effect and mask error enhanced factor (MEEF) are investigated through simulation. As pattern size decrease and lens NA gets bigger and bigger, the features on mask get smaller even below the wavelength of light and polarization related effects become one of the most critical issues. From comparison with results for 45nm HP patterning, we are able to suggest the reasonable process condition for HIL process.
Then, we have investigated the optimum BARC condition to make preparations for 32nm HP pattering.
In this paper, we will present comparison of attenuated phase shift mask and binary intensity mask at hyper-NA
immersion scanner which has been the main stream of DRAM lithography. Some technical issues will be reported for
polarized illumination in hyper-NA imaging. One att.PSM (Phase Shift Mask) and three types of binary intensity mask
are used for this experiment; those are ArF att.PSM ( MoSi:Å ), thick Cr ( 1030Å ) BIM (Binary Intensity Mask),
thin Cr ( 590Å ) BIM and multi layer ( Cr:740Å / MoSi:930Å ) BIM. Simulation and experiment with 1.35NA
immersion scanner are performed to study influence of mask structure, process margin and effect of polarization. Two
types of DRAM cell patterns are studied; one is an isolation pattern with a brick wall shape and another is a storage node
pattern with contact hole shape. Line and space pattern is also studied through 38nm to 50nm half pitch for this
experiment. Lithography simulation is done by in-house tool based on diffused aerial image model. EM-SUITE is also
used in order to study the influence of mask structure and polarization effect through rigorous EMF simulation.
Transmission and polarization effects of zero and first diffraction order are simulated for both att.PSM and BIM. First
and zero diffraction order polarization are shown to be influenced by the structure of masking film. As pattern size on
mask decreases to the level of exposure wavelength, incident light will interact with mask pattern, and then transmittance
changes for mask structure. Optimum mask bias is one of the important factors for lithographic performance. In the case
of att.PSM, negative bias shows higher image contrast than positive one, but in case of binary intensity mask, positive
bias shows better performance than negative one. This is caused by balance of amplitude between first diffraction order
and zero diffraction order light.
Process windows and mask error enhancement factors are measured with respect to various design rules, i.e., different k1
levels at fixed NA. In the case of one dimensional line and space pattern, thick Cr BIM shows the best performance
through various pitches. But in case of two dimensional DRAM cell pattern, it is difficult to find out the advantage of
BIM for sub-45nm. It needs further study for two dimensional patterns. Finally, it was observed that thick Cr binary
intensity mask for sub-45nm has advantage for one dimensional line and space pattern.
In this paper, we will present experimental results on 45nm node patterning of DRAM and some technical issues for
polarized illumination in hyper NA imaging. First, practical k1 limit of 1.2NA ArF immersion system is investigated
through experiment. Process window and mask error enhancement factors are measured with respect to various design
rules, i.e., different k1 levels at fixed NA. Reasonable process window and MEEF value of around 3 are achieved in
DRAM gate and isolation layers at around 0.28 k1 regime. It is obvious that feasibility of this lowered k1 was realized
by the help of polarized illumination when we compared the results with that of 60nm patterning at 0.93NA tool -
corresponding k1 is 0.29 - without polarized illumination. Then consideration about degree of polarization state must
come next to the benefit of polarized illumination. Input polarization state is changed by birefringence of lens or mask
materials but it is very difficult to correlate the birefringence level and critical dimension of patterns experimentally.
Double exposing method was contrived to measure the effect of degree of polarization on DICD. And we also measure
the polarization dependent transmittance of light on mask by using 1.2NA immersion scanner. As a result, birefringence
and mask feature interaction with light seems not to be a serious issue for 45nm hyper NA polarized imaging.
Making a sub-100 nm contact hole pattern is one of the difficult issues in semiconductor process. Compared with
another fabrication process, resist reflow process is a good method to obtain very high resolution contact hole. However
it is not easy to predict the actual reflow result by simulation because very complex physics and/or chemistry are
involved in resist reflow process. We must know accurate physical and chemical constant values and many fabrication
variables for better prediction. We made resist reflow simulation tool to predict approximate resist reflow as functions of
pitch, temperature, time, array, and so on. We were able to see the simulated top view, side view and the changed hole
size. We used Navier-Stokes equation for resist reflow. We had varied the reflow time, temperature, surface tension, and
3-dimensional volume effect for old model. However the photoresist adhesion is another very important factor that was
not included in the old model. So the adhesion effect was added on Navier-Stokes equation and found that there was a
distinctive difference in reflowed resist profile and the contact hole width compared to the case of no adhesion effect.
Resist reflow is a simple and cost effective technique by which the resist is baked above the glass transition temperature (Tg) after the typical contact hole pattern has been exposed, baked and developed. Resist reflow method can obtain very high resolution without the loss of process margin than any other resolution enhancement techniques that can make the same linewidth. But it is difficult to predict the results of the thermal flow and the process optimization. If the results of reflow process can be exactly predicted, we can save great time and cost. In order to optimize the layout design and process parameters, we develop the resist flow model which can predict the resist reflow tendency as a function of the contact hole size, initial shape and reflow temperature for the normal and elongated contact hole. The basic fluid equation is used to express the flow of resist and the variation of viscosity and density as a function of reflow temperature and time are considered. Moreover surface tension and gravity effects are also considered. In order to build a basic algorism, we assume that the fluid is incompressible, irrotational and Newtonian. First, we consider the boundary movement of side wall and we think the basic equations for free surface flow of fluid as 2-dimensional time-dependent Navier-Stokes equations with the mass conservation equation. Surface tension acting on the interface pressure difference and gravity force that enable the resist flow are also included.
There have been imposed quite incompatible requirements on lithographic simulation tool for OPC, that is it should be enough accurate and enough fast. Though diffused aerial image model (DAIM) has achieved these goals successfully, rapid transition of lithography into very low k1 and sub-resolution regime makes it very difficult to meet these goals without loss of any of speed or accuracy. In this paper we suggested new modeling method of resist process which is called heterogeneous diffusion of aerial image. First, various examples of CD discrepancy between experiment and simulation with DAIM are suggested. Then the theoretical background of new model is explained and finally CD prediction performance of new model is demonstrated in 60nm 0.29k1 patterning of real DRAM devices. Improved CD prediction capability of new model is observed in various critical patterning of DRAM.
512Mbit DRAM with 70 nm design rule was tailored using 0.31k1 ArF lithography technologies. Of the critical mask layers, four pattern layouts were demonstrated: brick wall, line/space, contact and line/contact patterns. For the sake of cost reduction, the conventional technologies were used. Results has shown that SLR (Single-Layer Resist) process, half-tone PSM and the conventional illuminations had a potential of manufacturing 70 nm DRAM. However, it was found that brick wall patterns had asymmetrical shape and total CD uniformity was out of target raging 9.2 nm through 16.3 nm depending mask layouts. We prospect that higher contrast resist and more elaborate resist process will address these problems sooner or later. In case the immersion lithography is not ready around the right time, the feasibility of 0.29k1 ArF lithography was studied through simulation and test, which represented that 0.29k1 technologies were likely to be applied for the development of 60 nm DRAM with the aid of RETs (Resolution Enhancement Technologies) including customized illumination and new hard mask process.
High aspect ration resist patterns with dimensions below 100 nm often bend, break or tear. These phenomena are generically called “resist pattern collapse”. Pattern collapse is a very serious problem in fine patterning of less than 100 nm critical dimension (CD), so that it decreases the yield. In order to mechanically analyze this phenomenon and create its simulator, two models have been made and compared. In this paper, various approaches with various analyses are made to understand pattern collapse. Also, the critical aspect ratio for 100 nm node, that determines whether pattern collapse happens or not, can be calculated with these approaches. Finally tear type caused by insufficiency of adhesion strength between the substrate and the resist is analyzed with a point of view of the surface free energy.
Dill’s ABC parameters are key parameters for the simulation of photolithography patterning. The exposure parameters of each resist should be exactly known to simulate the desired pattern. In ordinary extracting methods of Dill’s ABC parameters, the changed refractive index and the absorption coefficient of photoresist are needed during exposure process. Generally, these methods are not easy to be applied in a normal fab because of a difficulty of in-situ measuring. An empirical E0 (dose-to-clear) swing curve is used to extract ABC exposure parameters previously by our group. Dill’s ABC parameters are not independent from each other and different values of them would cause the dose to clear swing curve variation. By using the known relationship of ABC parameters, the experimental swing curves are to be matched with the simulated ones in order to extract the parameters. But sometimes this method is not easy in matching the procedure and performing simulation. This procedure would take much time for matching between the experimental data and the simulation by the naked eyes, and also the simulations are performed over and over again for different conditions. In this paper, Dill’s ABC parameters were extracted by applying the values, which are quantitatively determined by measuring the mean value, period, slope, and amplitude of the swing curve, to the neural network algorithm. As a result, Dill’s ABC parameters were able to rapidly and accurately extracted with some of the quantified values of the swing curve. This method of extracting the exposure parameters can be used in a normal fab so that any engineer can easily obtain the exposure parameters and apply them to the simulation tools.
In the step of developing lithography devices, VTRM (Variable Threshold Resist Model), aerial image based simulation, is useful to get feedback for a resist process margin. VTRM is also used to compensate for the mask pattern's OPE (Optical Proximity Effect) and to optimize the optical system rather than the full simulation method that requires all the process parameters. However, VTRM has shown some problems that the exposure dose and focus should be fixed in one special condition to improve the prediction accuracy and cannot be combined together in one equation for pattern's size and type variation. In this paper, a new simulation method that has more accuracy and wider applicability than the VTRM method was suggested. The new simulation method can represent the photolithography process with simple formula. The parameters of this formula are composed of exposure dose and defocus as input components, CD as output component, and all the resist processes are kept constant to keep consistency for other resist processes. The first technical improvement of this equation is to use process-matched aerial image derived from the fact that the aerial images at the top resist surface cannot represent the bulk resist energy distribution. The second one is to introduce a new concept TERM (Threshold Energy Resist Model). The energy threshold level is used instead of the aerial image's intensity threshold level in order to predict CDs. Energy threshold level can be simply found by the simple equation and an experiment. The simple equation consists of a mask edge opening energy, the mask edge image intensity, and a process factor.