Mr. Keiji Emoto Profile

Keiji Emoto

at Canon Inc

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Author

Publications (4)

Proceedings Article | 13 July 2017 Paper

Improved particle control for high volume semiconductor manufacturing for nanoimprint lithography

Masami Yonekawa, Takahiro Nakayama, Kazuki Nakagawa, Toshihiro Maeda, Yoichi Matsuoka, Keiji Emoto, Hisanobu Azuma, Yukio Takabayashi, Ali Aghili, Makoto Mizuno, Jin Choi, Chris Jones

Proceedings Volume 10454, 104540R (2017) https://doi.org/10.1117/12.2279365

KEYWORDS: Semiconducting wafers, Curtains, Polishing, Lithography, Liquids, Ceramics, Nanoimprint lithography, Particles, Control systems, Semiconductor manufacturing, Photomasks

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Proceedings Article | 20 October 2016 Paper

Nanoimprint system development and status for high volume semiconductor manufacturing

Hiromi Hiura, Yukio Takabayashi, Tsuneo Takashima, Keiji Emoto, Jin Choi, Phil Schumaker

Proceedings Volume 10032, 100320E (2016) https://doi.org/10.1117/12.2248363

KEYWORDS: Nanoimprint lithography, Overlay metrology, Particles, Photomasks, Semiconducting wafers, Curtains, Lithography, Semiconductors, Actuators, Data modeling

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Imprint lithography has been shown to be an effective technique for replication of nano-scale features. Jet and Flash Imprint Lithography* (J-FIL*) involves the field-by-field deposition and exposure of a low viscosity resist deposited by jetting technology onto the substrate. The patterned mask is lowered into the fluid which then quickly flows into the relief patterns in the mask by capillary action. Following this filling step, the resist is crosslinked under UV radiation, and then the mask is removed, leaving a patterned resist on the substrate. There are many criteria that determine whether a particular technology is ready for wafer manufacturing. For imprint lithography, recent attention has been given to the areas of overlay, throughput, defectivity, and mask replication. This paper reviews progress in these critical areas. Recent demonstrations have proven that mix and match overlay of less than 5nm can achieved. Further reductions require a higher order correction system. Modeling and experimental data are presented which provide a path towards reducing the overlay errors to less than 3nm. Throughput is mainly impacted by the fill time of the relief images on the mask. Improvement in resist materials provides a solution that allows 15 wafers per hour per station, or a tool throughput of 60 wafers per hour. Defectivity and mask life play a significant role relative to meeting the cost of ownership (CoO) requirements in the production of semiconductor devices. Hard particles on a wafer or mask create the possibility of inducing a permanent defect on the mask that can impact device yield and mask life. By using material methods to reduce particle shedding and by introducing an air curtain system, the lifetime of both the master mask and the replica mask can be extended. In this work, we report results that demonstrate a path towards achieving mask lifetimes of better than 1000 wafers. Finally, on the mask side, a new replication tool, the FPA-1100NR2 is introduced. Mask replication is required for nanoimprint lithography (NIL), and criteria that are crucial to the success of a replication platform include both particle control and IP accuracy. In particular, by improving the specifications on the mask chuck, residual errors of only 1nm can be realized.

Proceedings Article | 22 March 2016 Paper

Defectivity and particle reduction for mask life extension, and imprint mask replication for high-volume semiconductor manufacturing

Keiji Emoto, Fumio Sakai, Chiaki Sato, Yukio Takabayashi, Hitoshi Nakano, Tsuneo Takabayashi, Kiyohito Yamamoto, Tadashi Hattori, Mitsuru Hiura, Toshiaki Ando, Yoshio Kawanobe, Hisanobu Azuma, Takehiko Iwanaga, Jin Choi, Ali Aghili, Chris Jones, J. W. Irving, Brian Fletcher, Zhengmao Ye

Proceedings Volume 9777, 97770C (2016) https://doi.org/10.1117/12.2219036

KEYWORDS: Photomasks, Particles, Nanoimprint lithography, Lithography, Semiconductors, Control systems, Semiconductor manufacturing, Ultraviolet radiation, Optical lithography, Dry etching, Semiconducting wafers, Curtains, Liquids, Ceramics, Overlay metrology

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Proceedings Article | 22 March 2016 Paper

Nanoimprint system development and status for high-volume semiconductor manufacturing

Tsuneo Takashima, Yukio Takabayashi, Naosuke Nishimura, Keiji Emoto, Takahiro Matsumoto, Tatsuya Hayashi, Atsushi Kimura, Jin Choi, Philip Schumaker

Proceedings Volume 9777, 977706 (2016) https://doi.org/10.1117/12.2219001

KEYWORDS: Photomasks, Nanoimprint lithography, Lithography, Overlay metrology, Semiconductor manufacturing, Semiconductors, Semiconducting wafers, Particles, Capillaries, Ultraviolet radiation, Distortion, High volume manufacturing, Actuators

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