This research shows a 1mW Low Power and real-time imaging Tx/Rx communication system via RF-delay
smart Antenna using up to 10GHz UWB(Ultra WideBand) as a concept of Wireless Medical Telemetry Service
(WMTS). This UTCOMS (COMmunication System for Nano-scale USLI designed Endoscope using UWB technology)
results in less body loss(about 6~13dB) at high frequency, disposable and ingestible compact size of 5×10 mm2 and
multifunction, bidirectional communications, independent subsystem control multichannel, and high sensitivity smart
receiving antenna of three-dimensional image captured still and moving images.
The method for the multi-phase computer-generated-holography (CGH) design of reconfigurable chip or board level optical interconnection is discussed in this paper. First, an improved direct search (DS) algorithm for the multi-phase CGH design is presented. Using this method, the high quality multi-phase CGH can be calculated very quickly, and the computation complexity is much lower than the other algorithms such as the most popularly used DS method and SA method. Then, how to use this algorithm for the CGH design of the reconfigurable chip or board level optical interconnection is given.
In 1959, the physicist Richard Feynman advised his colleagues that "there's plenty of room at the bottom." He envisioned a discipline devoted to manipulating smaller and smaller units of matter. "I am not afraid," he wrote, "to consider the final question as to whether, ultimately -- in the great future -- we can arrange the atoms the way we want, the way very atoms, all the way down." However, in early 1980's the doom and gloom of silicon MOS transistors was foreshadowed and scaling of the humble MOS transistors beyond 140 nm appeared as the impossible dream. Manipulation of material science, the emergence of low-K material and copper technology together with new techniques in lithography and processing have paved the way for revised predication that has foreshadowed the feature sizes in the order of 20 nm - 30 nm will occur somewhere between 2012 and 2016. Coupled with these developments, nanochemists have began to probe into matter and now Nanochemistry is beginning to shape the future of new materials and better understand the unique properties of assemblies of atoms and molecules on a scale that range between that of individual building blocks and the bulk material, thus confirming Feynman's vision. At this level quantum effects can be significant and innovative ways of carrying out chemical reactions become possible.
Proc. SPIE. 5274, Microelectronics: Design, Technology, and Packaging
KEYWORDS: Semiconductors, Networks, Field programmable gate arrays, Computer programming, Computer simulations, Microelectronics, System integration, System on a chip, Standards development, Information operations
This paper presents the test and validation of FPGA based IP using the concept of remote testing. It demonstrates how a virtual tester environment based on a powerful, networked Integrated Circuit testing facility, aimed to complement the emerging Australian microelectronics based research and development, can be employed to perform the tasks beyond the standard IC test. IC testing in production consists in verifying the tested products and eliminating defective parts. Defects could have a number of different causes, including process defects, process migration and IP design and implementation errors. One of the challenges in semiconductor testing is that while current fault models are used to represent likely faults (stuck-at, delay, etc.) in a global context, they do not account for all possible defects. Research in this field keeps growing but the high cost of ATE is preventing a large community from accessing test and verification equipment to validate innovative IP designs. For these reasons a world class networked IC teletest facility has been established in Australia under the support of the Commonwealth government. The facility is based on a state-of-the-art semiconductor tester operating as a virtual centre spanning Australia and accessible internationally. Through a novel approach the teletest network provides virtual access to the tester on which the DUT has previously been placed. The tester software is then accessible as if the designer is sitting next to the tester. This paper presents the approach used to test and validate FPGA based IPs using this remote test approach.
The characterization of photodiode junction depth using laser beam induced current (LBIC) has long been ambiguous, due in part to the limited understanding behind the relevant physics governing this phenomena, and more importantly, the signal behavior for the various device geometries. In this work, the induced current behavior arising from the individual junction components that form the device for different geometric conditions is examined in detail. In particular, at low temperatures, the overall LBIC signal dependence to junction depth could be attributed to current crowding through the dominance of two competing current mechanisms which include a lateral current flow, Ilbic, and a transverse current flow, Iph. This study represents another step in the development towards a fully quantitative procedure for extracting junction depth and alternatively interpreting the current contributions arising from the individual junction components using LBIC.
A novel tunable optical filter structure based on an Opto-VLSI processor is proposed in this paper. The architecture is capable of dynamically tuning multiple pass-bands through reconfiguration of the size and shape of holographic diffractive gratings generated by the Opto-VLSI processor. Results for an experimental 3-passband tunable filter are presented confirming over 25dB of dynamic range and passband bandwidth of 2 nm.
MicroPhotonic broadband RF signal processors utilize the capability of photons to perform true-time delay processing at very low loss that is unattainable by conventional electronic methods. In this paper, we present a novel MicroPhotonic interference mitigation filter architecture that utilises a CMOS Si photoreceiver/VCSEL array in conjunction with a true-time-delay multi-cavity optical substrate to realise an adaptive transversal RF processor with arbitrary response. Results show that the proposed MicroPhotonic structure can synthesize adaptive interference mitigation with a shape factor (ratio of the -40dB bandwidth to the -3dB bandwidth) as low as 2 and passband ripples less than 0.25dB.
With the increasing demand on the access network in the local and
residential areas, there is a growing need for more scalable and
dynamic optical access network architectures. In this paper, variable optical splitter is utilized in the optical access network as branching device. By changing the number of branches at the variable optical splitter or tuning the optical power distribution between these branches, a more flexible architecture can be realized. This will enable more customers to access the network flexibly and dynamically. It also has the added advantage that it can provide link protection for the network.
Mobile multimedia communication has rapidly become a significant area of research and development constantly challenging boundaries on a variety of technological fronts. The processing requirements for the capture, conversion, compression, decompression, enhancement, display, etc. of increasingly higher quality multimedia content places heavy demands even on current ULSI (ultra large scale integration) systems, particularly for mobile applications where area and power are primary considerations. The ADC presented in this paper is designed for a vertically integrated (3D) system comprising two distinct layers bonded together using Indium bump technology. The top layer is a CMOS imaging array containing analogue-to-digital converters, and a buffer memory. The bottom layer takes the form of a configurable array processor (CAP), a highly parallel array of soft programmable processors capable of carrying out complex processing tasks directly on data stored in the top plane. This paper presents a ADC scheme for the image capture plane. The analogue photocurrent or sampled voltage is transferred to the ADC via a column or a column/row bus. In the proposed system, an array of analogue-to-digital converters is distributed, so that a one-bit cell is associated with one sensor. The analogue-to-digital converters are algorithmic current-mode converters. Eight such cells are cascaded to form an 8-bit converter. Additionally, each photo-sensor is equipped with a current memory cell, and multiple conversions are performed with scaled values of the photocurrent for colour processing.
In this paper we propose an on-pixel Analog-to-Digital converter based on pulse frequency modulation (PFM) scheme. This PFM based converter presents a very viable solution for pixel level based ADC. It uses a very simple and robust circuit that can be implemented in a compact area resulting in a 23% fill-factor. The low-light performance of the PFM converter is improved by using a wider counting period. By modifying the counting period, it is possible to change the saturation level of the ADC and hence improve the dynamic range of the sensor. Image lag is eliminated in the PFM On-pixel ADC since a reset of the photodetector is performed after the conversion period. In addition, the PFM on-pixel ADC has a very important advantage: it is insensitive to variations of the supply and reference voltages. The pixel based ADC has been designed and fabricated using CMOS 0.25micrometers technology.
The Australian Commonwealth government recently announced a grant of $4.75 million as part of a $13.5 million program to establish a world class networked IC tele-test facility in Australia. The facility will be based on a state-of-the-art semiconductor tester located at Edith Cowan University in Perth that will operate as a virtual centre spanning Australia. Satellite nodes will be located at the University of Western Australia, Griffith University, Macquarie University, Victoria University and the University of Adelaide. The facility will provide vital equipment to take Australia to the frontier of critically important and expanding fields in microelectronics research and development. The tele-test network will provide state of the art environment for the electronics and microelectronics research and the industry community around Australia to test and prototype Very Large Scale Integrated (VLSI) circuits and other System On a Chip (SOC) devices, prior to moving to the manufacturing stage. Such testing is absolutely essential to ensure that the device performs to specification. This paper presents the current context in which the testing facility is being established, the methodologies behind the integration of design and test strategies and the target shape of the tele-testing Facility.
Camera-on-a-CMOS chip will be an inevitable component of future intelligent vision systems. However, up till now, the dominant format of data in imaging devices is still analog. The analog photocurrent or sampled voltage is transferred to the ADC via a column or a column/row bus. Moreover, in the active pixel configuration the area occupied by circuitry reduces significantly the fill factor, so that there are heavy constraints imposed on the size of the circuits used. In this paper a concept of back illuminated focal plane is presented. The system consists of two chips bonded face to face using Indium bumps. The top chip, which is the seeing chip, is thinned and the light signal is applied to the bottom surface. The bottom chip is the processing chip and it contains a distributed array of analog-to digital converters. As the seeing chip is fully dedicated to photosensors the fill factor can be increased from 25-40% possible on a single plane to over 95% with two planes. The analog-to-digital converters are algorithmic current-mode converters, where one-bit cell is implemented in the processing area facing one-pixel. Eight such cells are cascaded to form an 8-bit converter. As a result, a fully digital pixel readout is obtained.
In the span of a few years, mobile multimedia communication has rapidly become a significant area of research and development constantly challenging boundaries on a variety of technological fronts. Video compression, a fundamental component for most mobile multimedia applications, generally places heavy demands in terms of the required processing capacity. Hardware implementations of typical modern hybrid codecs require realisation of components such as motion compensation, wavelet transform, quantisation, zerotree coding and arithmetic coding in real-time. While the implementation of such codecs using a fast generic processor is possible, undesirable trade-offs in terms of power consumption and speed must generally be made. The improvement in power consumption that is achievable through the use of a slow-clocked massively parallel processing environment, while maintaining real-time processing speeds, should thus not be overlooked. An architecture to realise such a massively parallel solution for a zerotree entropy coder is, therefore, presented in this paper.
In this paper, a CMOS circuit for flexible read-out of imagers is proposed allowing random access, sequential access and window based access to the pixels. The circuit has been implemented within a CMOS imager using 0.7 micrometers technology. It is shown that this versatile read-out technique is obtained with only 8% increase in the silicon area as compared to the often used sequential read-out technique. The read-out circuit is fully digital, which makes it more robust against sizing mismatch. The circuit operates at a maximum frequency of 50 MHz which makes it very attractive for real time applications.
Proc. SPIE. 3893, Design, Characterization, and Packaging for MEMS and Microelectronics
KEYWORDS: Logic, Switching, Gallium arsenide, Microelectronics, Very large scale integration, Transistors, Integrated circuits, Field effect transistors, Digital electronic circuits, Digital electronics
There are numerous sources of noise present in the VLSI integrated circuits. A function that can measure the ability of a digital logic circuit to operate error-free in a noisy environment is noise margin which can be define in several ways from the transfer characteristic of the logic circuit. It is critical to be able to precisely evaluate a noise margin for Gallium Arsenide circuits, as its value is usually limited to the extent that only NOR gates are allowed in DCFL digital circuits and NAND gates, where stacked pull down transistors would be required, are excluded. In the paper, the best-case and worst-case static noise margin are discussed and it is shown that not only the load but also the noise voltage has to be included when evaluating a transfer function. Fortunately, the best-case noise margin can still be calculated with the nose free transfer function. But the more useful worst-case noise margin is shown to depend on the transfer function including the noise source. Therefore, as was already pointed out by Lohstroh for CMOS circuits, the best way to calculate the noise margin is to start a quasi-static transient simulation with all noise sources being zero and by increasing the amplitudes of the noise sources slowly compared to the switching speed of the logic circuits. The worst-case noise margin is then found as the noise amplitude at which the chain exhibits a malfunction. Since an infinitely long chain is sown to be equivalent to a flip-flop the flip-flop can be used for the simulation instead. The examples of an inverter and an AND gate illustrate the theory presented.
There are many applications where ultra-fast digital arithmetic circuits are required. At ultra-high speeds a considerable part of power is dissipated within a clock generation and distribution syste. At the same time, at gigahertz frequencies the clock skew becomes a factor limiting the speed of the system. This paper presents a design methodology for highly pipelined, self-timed circuits and systems suitable for multimedia applications using Gallium Arsenide MESFET as the base technology implementation of latched logic design style (PDLL, LCFL). The use of latched logic together with the absence of the global clock provides for low power dissipation while maintaining very high speed of the system. The main advantage of the latched structure is provided by the feedback which ensures that the nose margin is higher than for a simple Direct Coupled FET Logic gate. This enables to use serial connections of the E-type transistors in the pull-down section. Therefore, in GaAs latched logic it is possible to implement logic gates based on the AND function which have several control inputs and that they generate at least one control signal for handshaking. For the typical 4- phase handshaking protocol the input signals are enable and start and the required generated signal is Done. In the paper the appropriate modifications of the handshaking protocol to accommodate the properties of the latched logic GaAs circuits is presented an the inherent latching property of LCFL is exploited to eliminate latches separate from the logic blocks in the classic pipeline. Several circuit examples demonstrate the advantages of the proposed circuit techniques.
In many applications, such as multimedia and on-chip camera, there is a need for the production of low power, low weight and low cost integrated circuits. Several CMOS vision chips have been proposed in the literature. Some limitations of conventional 2D architectures are discussed and a new 3D generation of vision chips is presented and reviewed in this paper. As a result of this analysis, some conclusions on the advantages and limitations of 2D vision chips and the feasibility of the 3D approach are explored.
Motion detection, for collision avoidance,using VLSI monolithic smart sensors that mimic insect vision have ben reported for some time. Due to the parallel processing required by insect vision, actual chip implementations have tended to be limited to 1D arrays of integrated photodetectors, or modest 2D arrays. This paper reviews our progress, to date, and examines some of the issues that lie ahead for large 2D insect vision arrays.
Insects tend to detect motion rather than images and this together with inherent parallelism in their visual architecture, leads to an efficient and compact means of collision avoidance. A VLSI implementation of a smart microsensor that mimics the early visual processing stage in insects has been developed. The system employs the `smart sensor' paradigm in that the detectors and processing circuitry are integrated on one chip. The IC is ideal for motion detectors, particularly collision avoidance tasks, as it essentially detects the speed, bearing and time-to-impact of a moving object. The Horridge model for insect vision has been directly mapped into VLSI and therefore the IC truly exploits the beauty of nature in that the insect eye is so compact with parallel processing, enabling compact motion detection without the computational overhead of intensive imaging, full image extraction and interpretation. This world-first has exciting applications in areas such as anti- collision for automobiles and autonomous robots.
Proc. SPIE. 2950, Advanced Focal Plane Arrays and Electronic Cameras
KEYWORDS: Photodetectors, Optical amplifiers, Visual process modeling, Sensors, Interference (communication), Motion detection, Very large scale integration, Analog electronics, Motion models, Digital electronics
Implementing motion detection algorithms using analog VLSI techniques has proven to be a challenging task due to several obstacles, including the limitations of analog VLSI, the algorithmic limitations brought forward by complex motion detection schemes, and the effect of various types of noise. Insect vision has been an inspiring model for motion detectors, as insects heavily rely on motion detection for navigation, and the natural complexity of their neuro-visual circuitry is also less than that of vertebrates. In an effort to implement the so called template model of insect vision, a comparative study of various analog differentiators was undertaken by implementing different candidates on a test chip. Based on the results, a 64 by 4 motion detector has been designed and fabricated. The chip is designed in a 0.8 micrometer 3M-1P CMOS process, and the 2-D array occupies an area of 1.5 multiplied by 3.1 mm2. Each cell comprises a bipolar-mode photodetector, an adaptive amplifier, the improved analog differentiator, and thresholding circuits.
KEYWORDS: Infrared detectors, Infrared sensors, Extremely high frequency, Visual process modeling, Visualization, Sensors, Gallium arsenide, Very large scale integration, Infrared radiation, Digital electronics
With regard to obstacle avoidance, a paradigm shift from technology centered solutions to technology independent solutions is taking place. This trend also gives rise to a shift from function specific solutions to multifunctional solutions. A number of existing approaches are reviewed and a case study of a biologically inspired insect vision model is used to illustrate the new paradigm. The insect vision model leads to the realization of a sensor that is low in complexity, high in compactness, multifunctional and technology independent. Technology independence means that any front end technology, resulting in either optical, infrared or mm wave detection, for example, can be used with the model. Each technology option can be used separately or together with simple data fusion. Multifunctionality implies that the same system can detect obstacles, perform tracking, estimate time-to-impact, estimate bearing, etc. and is thus non-function specific. Progress with the latest VLSI realization of the insect vision sensor is reviewed and gallium arsenide is proposed as the future medium that will support a multifunctional and multitechnology fusion of optical, infrared, millimeter wave, etc. approaches. Applications are far reaching and include autonomous robot guidance, automobile anti-collision warning, IVHS, driver alertness warning, aids for the blind, continuous process monitoring/web inspection and automated welding, for example.
An analog VLSI implementation of a smart microsensor that mimics the early visual processing stage in insects is described with an emphasis on the overall concept and the front- end detection. The system employs the `smart sensor' paradigm in that the detectors and processing circuitry are integrated on the one chip. The integrated circuit is composed of sixty channels of photodetectors and parallel processing elements. The photodetection circuitry includes p-well junction diodes on a 2 micrometers CMOS process and a logarithmic compression to increase the dynamic range of the system. The future possibility of gallium arsenide implementation is discussed. The processing elements behind each photodetector contain a low frequency differentiator where subthreshold design methods have been used. The completed IC is ideal for motion detection, particularly collision avoidance tasks, as it essentially detects distance, speed & bearing of an object. The Horridge Template Model for insect vision has been directly mapped into VLSI and therefore the IC truly exploits the beauty of nature in that the insect eye is so compact with parallel processing, enabling compact motion detection without the computational overhead of intensive imaging, full image extraction and interpretation. This world-first has exciting applications in the areas of automobile anti- collision, IVHS, autonomous robot guidance, aids for the blind, continuous process monitoring/web inspection and automated welding, for example.