Since 2008, we have been presenting some papers regarding CMOS 45nm logic gate patterning activity to
reduce CD dispersion. After a global CD budget evaluation at SPIE08, we have been focusing on Intrafield CD
corrections using Dose MapperTM. The story continues and since then we have pursued our intrafield characterisation
and focus on ways to get Dose MapperTM dose recipe created before the first silicon is coming. In fact 40nm technology
is already more demanding and we must be ready with integrated solutions for 32/28nm node.
Global CD budget can be divided in Lot to Lot, Wafer to Wafer, Intra wafer and Intra field component. We
won't talk here about run to run solutions which are put in place for Lot to Lot and Wafer to Wafer. We will emphasize
on the intrafield / intrawafer process corrections and outline process compensation control and strategy. A lot of papers
regarding intrafield CD compensation are available in the litterature but they do not necesserally fit logic manufacturing
needs or possibilities. We need to put similar solutions in place which are comprehensive and flexible. How can we
correct upfront an Etch chamber CD profile combined with a mask and scanner CD signature? How can we get intrafield
map from random logic devices? This is what we will develop in this paper.
CMOS 45nm technology, and especially the logic gate patterning has led us to hunt for every nanometer we
could found to reach aggressive targets in term of overall CD budget. We have presented last year a paper ("Process
Control for 45 nm CMOS logic gate patterning " - B. Le Gratiet SPIE2008; 6922-33) showing the evaluation of our
process at that time. One of the key item was the intrafield control. Preliminary data were presented regarding intrafield
CD corrections using Dose MapperTM. Since then, more work has been done in this direction and not only for the GATE
Depending on reticle specification grade, process MEEF and scanner performance, intrafield CD variation can
reach quite high CD ranges and become a non negligeable part of the overall budget. Although reticles can achieve very
good level of CD uniformity, they all have their own "footprint" which will becomes a systematic error. The key point
then is to be able to measure this footprint and correct for it on the wafer. Scanners suppliers provide tools like Dose
MapperTM to modify the intrafield exposure dose profile. Generating and using a proper exposure "subrecipe" requires
intrafield in-line control needs on production wafers. This paper present a status of our work on this subject with some
results related to global gate CMOS 45nm CD variability improvement including etch process compensation with Dose
This paper present an evaluation of our CMOS 45nm gate patterning process performance based on immersion
lithography in a production environment. A CD budget breakdown is shown detailing lot to lot, wafer to wafer,
intrawafer, intrafield and proximity CD uniformity characterization. Emphasis is given on scatterometry library
development and deployment. We also look more into detail to focus effect on CD control. Finally status of overlay
performance with immersion lithography is also presented.
CMOS 65nm technology node requires the introduction of advanced materials for critical patterning operations. The
study is focused on the multilayer Anti Reflective Coating (ARC) stack, used in photolithography, for the gate patterning
such as Advanced Patterning Film (APF). The interest on this new and complex ARC stack lies in the benefit to
guarantee low CD dispersion thanks to a better reflectivity control and resist budget which leads to a larger lithographic
process window. However, it implies numerous metrology challenges.
The paper deals with the challenges of monitoring the gate Critical Dimension (CD) on this stack. The validation of
the scatterometry model versus stack thicknesses and indexes variations, through experiments, is also described. The
final result is the complete characterization of the materials for thickness and scatterometry CD control, for photo feedback
and for etch feed-forward deployment in an industrial mode.
The analysis shows that scatterometry measurements on a standard 65 nm gate process ensure a better effectiveness
than the CD Scanning Electron Microscopy (SEM) ones when injected in the Advanced Process Control (APC) system
from photo to etch.