Dr. Katsushi Nakano Profile

Dr. Katsushi Nakano

at Nikon Corp

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Author

Publications (17)

Proceedings Article | 13 March 2012 Paper

High hydrophobic topcoat approach for high volume production and yield enhancement of immersion lithography

Natsuko Sagawa, Katsushi Nakano, Yuuki Ishii, Kazunori Kusabiraki, Motoyuki Shima

Proceedings Volume 8326, 832627 (2012) https://doi.org/10.1117/12.916271

KEYWORDS: Scanners, Semiconducting wafers, Immersion lithography, Fluorine, Polymers, Photoresist processing, Inspection, Particles, Manufacturing, Bridges

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Proceedings Article | 10 March 2010 Paper

Topcoat-less resist approach for high volume production and yield enhancement of immersion lithography

Katsushi Nakano, Rei Seki, Tadamasa Kawakubo, Yoshihiro Maruta, Toshiyuki Sekito, Kenichi Shiraishi, Toshihiko Sei, Tomoharu Fujiwara, Tsunehito Hayashi, Yasuhiro Iriuchijima, Soichi Owa

Proceedings Volume 7640, 76400X (2010) https://doi.org/10.1117/12.846520

KEYWORDS: Semiconducting wafers, Photoresist processing, Immersion lithography, Double patterning technology, Atrial fibrillation, Polymers, Particles, Inspection, Printing, Scanning electron microscopy

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Double patterning (DP) is the first candidate for extension of ArF immersion lithography, and topcoat-less (TC-less) process is an attractive process candidate compared to a topcoat process because it can make DP process simpler and reduce the chip manufacturing cost. To make the DP process viable, TC-less process performance including defectivity, auto focus (AF) and overlay performance must be validated. Nikon's latest volume production immersion lithography tool (S620D), was used for TC-less process evaluation. While S620D shows good defectivity results with both topcoat and TC-less process at 700mm/s scan speed, TC-less process showed slight improvement in defectivity compared to topcoat process. One reason being that TC-less process can suppress topcoat originated defect such as topcoat blister. The second reason is that TC-less resist can attain higher hydrophobicity than topcoat. Higher hydrophobicity is advantageous for high speed scanning because of stable movement of water meniscus, resulting in better defectivity performance. Defectivity results showed clear correlation to dynamic receding contact angle (D-RCA). Blob defect reduction is one of the challenges with TC-less resist process, because hydrophobic surface repels rinse water applied during development rinse process hence generating blob defect. However, the recent material improvements of TC-less resist have overcome this challenge and showed excellent blob defect performance. The hydrophobicity control during development process is the key factor in defect reduction. Wafer edge process is also very important for immersion lithography. The preferable wafer edge treatment for both TCless and topcoat process is to maintain uniform hydrophobicity over the entire wafer including wafer edge. While topcoat can be removed perfectly by development, unexposed TC-less resist remains on the wafer edge. WEE (wafer edge exposure) process can remove the excess resist after exposure, it's effectiveness was confirmed through experimental results. AF and overlay repeatability was evaluated on both topcoat and TC-less process; similar and sufficient performance was obtained on both processes. Based on cost of ownership calculations it is believed a 30% material cost and 10% track hardware cost reduction is feasible. These evaluations provide convincing evidence that TC-less process is ready for 32nm generation and beyond.

Proceedings Article | 1 April 2009 Paper

Practical implementation of immersion resist materials

Hamid Khorram, Katsushi Nakanob, Tomoharu Fujiwara, Yasuhiro Iriuchijima, Y. Ishii, Natsuko Sagawa, Tadamasa Kawakubo, Shirou Nagaoka

Proceedings Volume 7273, 72732V (2009) https://doi.org/10.1117/12.814946

KEYWORDS: Semiconducting wafers, Scanners, Photoresist processing, Manufacturing, Immersion lithography, Lithography, Liquids, Particles, Inspection, Materials processing

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Immersion lithography has gone through its first phase of introduction and acceptance as the main solution for critical layer lithography for 45nm node and beyond. In this phase, the industry has found that immersion technology has its own unique challenges associated with introducing water as a medium between the projection lens and wafer. Resist process qualification is once again under the spot light. Due to the rapid introduction of immersion technology resist suppliers did not have sufficient time to reformulate their standard ArF resist processes to be compatible with water while at the same time satisfying critical imaging, etching and other requirements. For this reason a barrier (topcoat) had to be introduced in order to prevent resist leaching as well as to produce a more desirable surface for water to glide over. Introducing a top-coat created challenges for all parties involved: scanner manufacturers resist vendors and the end users. Since each manufacturer has its own unique technology for introducing immersion water, top-coat/resist processes needed not only to meet the end users' performance criteria but also meet each scanner manufacturer's requirements. Therefore material screening process and process evaluation became an important factor in immersion technology processes. Defectivity became the primary criterion for the resist process. The responsibility of the scanner manufacturer is twofold: first, to produce a system compatible with many different resist processes while not introducing additional defects, and second, to give resist manufacturers clear and concise requirements for achieving performance. In this paper we show how we have met the industry's needs in this area. First, we discuss the importance of material screening, including requirements for hydrophobicity, leaching, and peeling. Second, we present defectivity and other experimental data from practical materials that fulfill all requirements. Cases will be shown wherein an immersion process using commercially available resist processes introduces no additional defects. Several of these now do not require a topcoat. We therefore show that the industry's needs have been met with both topcoat and topcoat-less processes.

Proceedings Article | 16 March 2009 Paper

Control and reduction of immersion defectivity for yield enhancement at high volume production

Katsushi Nakano, Rei Seki, Toshiyuki Sekito, Masato Yoshida, Tomoharu Fujiwara, Yasuhiro Iriuchijima, Soichi Owa

Proceedings Volume 7274, 72741P (2009) https://doi.org/10.1117/12.814238

KEYWORDS: Semiconducting wafers, Particles, Head-mounted displays, Inspection, Silicon, Contamination, Immersion lithography, Scanning electron microscopy, Photoresist processing, Manufacturing

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Volume device manufacturing using immersion lithography is widely accepted as the solution for patterning IC features below 40 nm half pitch. In order to ensure high yield and steady productivity tight control of defectivity is essential. A major source of defects and tool contamination is the particles introduced by incoming wafers. Particles can be categorized in two groups: particles attached to wafer surface or residues on the wafer edge. Surface or edge peeling of topcoats can also be a source of particle. Adhesion force between topcoat or topcoat-less (TC-less) resist and wafer is one of the most important parameter for particle reduction. Peeling test results proved that TC-less resist has better adhesion performance than topcoat. One of the most commonly used adhesion promoting material is hexamethyldisilazane (HMDS). Application condition of this material is an important factor in preventing wafer edge and surface topcoat peeling. Studies have shown lower temperature and longer application of HMDS shows better adhesion result. Maintaining a clean wafer surface is also a very important factor for particle reduction. Pre-rinse, which can rinse off particles before exposure, was evaluated and the efficiency was confirmed. Edge particles are more effectively reduced by pre-rinse, because weakly attached topcoat and wafer edge residues were effectively removed by pre-rinse. For further particle reduction, edge residue reduction and cut line roughness improvement were evaluated and their effectiveness was confirmed. Lower cut position achieved improved particle counts on both topcoat and TC-less resist; more frequent contact between water and cut-line can weaken the adhesion and consequently peel off topcoat or TC-less resist. Finally the relationship between defectivity and hydrophobicity is analyzed, high Receding Contact Angle (RCA) showed better defectivity result. Topcoat and TC-less process is compared for each defectivity reduction methodology and for each category TC-less process always showed lower defectivity level and less sensitivity to process conditions, indicating that TC-less process is safer and more robust than topcoat process.

Proceedings Article | 16 March 2009 Paper

Immersion-cluster uptime enhancement technology toward high-volume manufacturing

R. Tanaka, T. Fujiwara, K. Nakano, S. Wakamizu, H. Kyouda

Proceedings Volume 7274, 72743M (2009) https://doi.org/10.1117/12.814112

KEYWORDS: Contamination, Semiconducting wafers, Particles, Bridges, Thin film coatings, High volume manufacturing, Coating, Immersion lithography, Process control, Image filtering

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Proceedings Article | 4 December 2008 Paper

193-nm immersion lithography for high volume manufacturing using novel immersion exposure tool and coater/developer system

Shinya Wakamizu, Hideharu Kyouda, Katsushi Nakano, Tomoharu Fujiwara

Proceedings Volume 7140, 714039 (2008) https://doi.org/10.1117/12.804675

KEYWORDS: Immersion lithography, Semiconducting wafers, Particles, Coating, Lithography, Photoresist processing, Thin film coatings, Scanners, Scanning electron microscopy, Semiconductors

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Proceedings Article | 11 April 2008 Paper

The rapid introduction of immersion lithography for NAND flash: challenges and experience

Chan-Tsun Wu, Hung Ming Lin, Wei-Ming Wu, Meng-Hsun Chan, Benjamin Lin, Kuan-Heng Lin, Andrew Hazelton, Toshio Ohhashi, Katsushi Nakano, Yasuhiro Iriuchijima, Chunhsin Lee, Long Hung

Proceedings Volume 6924, 69241A (2008) https://doi.org/10.1117/12.772448

KEYWORDS: Photoresist materials, Semiconducting wafers, Particles, Scanners, Line width roughness, Immersion lithography, Lithography, Critical dimension metrology, Coating, Defect inspection

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Proceedings Article | 4 April 2008 Paper

Process development for high scan speed ArF immersion lithography

Nobuji Matsumura, Norihiko Sugie, Kentaro Goto, Koichi Fujiwara, Yoshikazu Yamaguchi, Hirokazu Tanizaki, Katsushi Nakano, Tomoharu Fujiwara, Shinya Wakamizu, Hirofumi Takeguchi, Hiroshi Arima, Hideharu Kyoda, Kosuke Yoshihara, Junichi Kitano

Proceedings Volume 6923, 69230D (2008) https://doi.org/10.1117/12.771795

KEYWORDS: Lithography, Immersion lithography, Thin film coatings, 193nm lithography, Semiconducting wafers, Bridges, Defect inspection, Photoresist processing, Line width roughness, Semiconductors

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Proceedings Article | 17 March 2008 Paper

Immersion defectivity study with volume production immersion lithography tool for 45 nm node and below

Katsushi Nakano, Shiro Nagaoka, Masato Yoshida, Yasuhiro Iriuchijima, Tomoharu Fujiwara, Kenichi Shiraishi, Soichi Owa

Proceedings Volume 6924, 692418 (2008) https://doi.org/10.1117/12.772270

KEYWORDS: Particles, Semiconducting wafers, Photoresist processing, Inspection, Bridges, Coating, Printing, Photomasks, Immersion lithography, Materials processing

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Proceedings Article | 3 May 2007 Paper

Current status of water immersion lithography and prospect of higher index method

Soichi Owa, Katsushi Nakano, Hiroyuki Nagasaka, Hirotaka Kohno, Yasuhiro Ohmura, Martin McCallum

Proceedings Volume 6533, 653304 (2007) https://doi.org/10.1117/12.731916

KEYWORDS: Semiconducting wafers, Imaging systems, Double patterning technology, Water, Immersion lithography, Manufacturing, Lithography, Refractive index, Photoresist developing, Thin film coatings

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Proceedings Article | 29 March 2007 Paper

Immersion defectivity control by optimizing immersion materials and processes

Katsushi Nakano, Hiroshi Kato, Soichi Owa

Proceedings Volume 6519, 65190D (2007) https://doi.org/10.1117/12.711466

KEYWORDS: Particles, Semiconducting wafers, Bridges, Photoresist processing, Immersion lithography, Scanning electron microscopy, Photomasks, Signal attenuation, Materials processing, Defect detection

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Proceedings Article | 26 March 2007 Paper

Immersion defectivity study with volume production immersion lithography tool

Katsushi Nakano, Hiroshi Kato, Tomoharu Fujiwara, K. Shiraishi, Yasuhiro Iriuchijima, Soichi Owa, Irfan Malik, Steve Woodman, Prasad Terala, Christine Pelissier, Haiping Zhang

Proceedings Volume 6520, 652016 (2007) https://doi.org/10.1117/12.711464

KEYWORDS: Semiconducting wafers, Particles, Immersion lithography, Inspection, Wafer inspection, Bridges, Photoresist processing, Optical lithography, Calibration, Defect inspection

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ArF immersion lithography has become accepted as the critical layer patterning solution for lithography going forward. Volume production of 55 nm devices using immersion lithography has begun. One of the key issues for the success of volume production immersion lithography is the control of immersion defectivity. Because the defectivity is influenced by the exposure tool, track, materials, and the wafer environment, a broad range of analysis and optimization is needed to minimize defect levels. Defect tests were performed using a dedicated immersion cluster consisting of a volume production immersion exposure tool, Nikon NSR-S609B, having NA of 1.07, and a resist coater-developer, TEL LITHIUS i+. Miniaturization of feature size by immersion lithography requires higher sensitivity defect inspection. In this paper, first we demonstrate the high sensitivity defect measurement using a next generation wafer inspection system, KLA-Tencor 2800 and Surfscan SP2, on both patterned and non-patterned wafers. Long-term defect stability is very important from the viewpoint of device mass production. Secondly, we present long-term defectivity data using a topcoat-less process. For tool and process qualification, a simple monitor method is required. Simple, non-pattern immersion scanned wafer measurement has been proposed elsewhere, but the correlation between such a non-pattern defect and pattern defect must be confirmed. In this paper, using a topcoat process, the correlation between topcoat defects and pattern defects is analyzed using the defect source analysis (DSA) method. In case of accidental tool contamination, a cleaning process should be established. Liquid cleaning is suitable because it can be easily introduced through the immersion nozzle. An in-situ tool cleaning method is introduced. A broad range of optimization of tools, materials, and processes provide convincing evidence that immersion lithography is ready for volume production chip manufacturing.

Proceedings Article | 11 April 2006 Paper

Low leaching and low LWR photoresist development for 193 nm immersion lithography

Nobuo Ando, Youngjoon Lee, Takayuki Miyagawa, Kunishige Edamatsu, Ichiki Takemoto, Satoshi Yamamoto, Yoshinobu Tsuchida, Keiko Yamamoto, Shinji Konishi, Katsushi Nakano, Fujiwara Tomoharu

Proceedings Volume 6153, 615322 (2006) https://doi.org/10.1117/12.655586

KEYWORDS: Line width roughness, Polymers, Diffusion, Semiconducting wafers, Immersion lithography, Photoresist materials, Lithography, Photoresist developing, Scanners, Molecules

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With no apparent showstopper in sight, the adoption of ArF immersion technology into device mass production is not a matter of 'if' but a matter of 'when'. As the technology matures at an unprecedented speed, many of initial technical difficulties have been cleared away and the use of a protective layer known as top coat, initially regarded as a must, now becomes optional, for example. Our focus of interest has also sifted to more practical and production related issues such as defect reducing and performance enhancement. Two major types of immersion specific defects, bubbles and a large number of microbridges, were observed and reported elsewhere. The bubble defects seem to decrease by improvement of exposure tool. But the other type defect - probably from residual water spots - is still a problem. We suspect that the acid leaching from resist film causes microbridges. When small water spots were remained on resist surface after exposure, acid catalyst in resist film is leaching into the water spots even though at room temperature. After water from the spot is dried up, acid molecules are condensed at resist film surface. As a result, in the bulk of resist film, acid depletion region is generated underneath the water spot. Acid catalyzed deprotection reaction is not completed at this acid shortage region later in the PEB process resulting in microbridge type defect formation. Similar mechanism was suggested by Kanna et al, they suggested the water evaporation on PEB plate. This hypothesis led us to focus on reducing acid leaching to decrease residual water spot-related defect. This paper reports our leaching measurement results and low leaching photoresist materials satisfying the current leaching requirements outlined by tool makers without topcoat layer. On the other hand, Nakano et al reported that the higher receding contact angle reduced defectivity. The higher receding contact angle is also a key item to increase scan speed. The effort to increase the receding contact angle become very important issue for not only defectivity but also scanner throughput. Some of our experimental results along this line of study are also included in the report. The last topic covered is LWR (Line Width Roughness) as an essential leverage for performance improvement, especially for the smaller CD that immersion lithography is aiming to define. Our recent effort to find effect and working concept to reduce LWR with low leaching materials is also described.

Proceedings Article | 11 April 2006 Paper

Defect studies of resist process for 193nm immersion lithography

Tomoyuki Ando, Katsumi Ohmori, Satoshi Maemori, Toshikazu Takayama, Keita Ishizuka, Masaaki Yoshida, Tomoyuki Hirano, Jiro Yokoya, Katsushi Nakano, Tomoharu Fujiwara, Soichi Owa

Proceedings Volume 6153, 615309 (2006) https://doi.org/10.1117/12.656164

KEYWORDS: Semiconducting wafers, Photoresist processing, Immersion lithography, Resonance energy transfer, Lithography, Materials processing, Bridges, 193nm lithography, Molecular bridges, Lens design

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Proceedings Article | 11 April 2006 Paper

Immersion topcoat and resist material improvement study by using immersion scanner

Hiroki Nakagawa, Kenji Hoshiko, Motoyuki Shima, Shiro Kusumoto, Tsutomu Shimokawa, Katsushi Nakano, Tomoharu Fujiwara, Soichi Owa

Proceedings Volume 6153, 61530D (2006) https://doi.org/10.1117/12.655541

KEYWORDS: Semiconducting wafers, Scanners, Water, Lithography, Immersion lithography, Resonance energy transfer, Photoresist processing, Photoresist materials, Silicon, Chemical analysis

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Proceedings Article | 21 March 2006 Paper

Analysis and improvement of defectivity in immersion lithography

Katsushi Nakano, Soichi Owa, Irfan Malik, Tetsuya Yamamoto, Somnath Nag

Proceedings Volume 6154, 61544J (2006) https://doi.org/10.1117/12.656195

KEYWORDS: Semiconducting wafers, Coating, Scanning electron microscopy, Immersion lithography, Particles, Bridges, Inspection, Resonance energy transfer, Photoresist processing, Defect inspection

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Proceedings Article | 15 March 2006 Paper

Current status and future prospect of immersion lithography

Soichi Owa, Hiroyuki Nagasaka, Katsushi Nakano, Yasuhiro Ohmura

Proceedings Volume 6154, 615408 (2006) https://doi.org/10.1117/12.656887

KEYWORDS: Optics manufacturing, Semiconducting wafers, Water, Resonance energy transfer, Double patterning technology, Immersion lithography, Scanners, Combined lens-mirror systems, Particles, Projection systems

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Showing 5 of 17 publications

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