Process Control Solutions ,
Multivariate analysis & Deep Learning ,
Design of Experiments ,
Defect Inspection & metrology ,
PWQ & EM Simulations ,
New product development
Natural physical phenomena occurring at length scales of a few nm in EUV lithography give rise to variation in photoresist images: edge, width, and top roughness, feature-to-feature CD or shape variability, edge placement errors, etc. The most damaging are stochastic printing failures caused by undesirable film thickness loss, admitting etch in line regions, or film thickness gain, preventing etch in space regions. In this work, we begin from analysis of well-calibrated rigorous physical stochastic EUV lithography models to study nanoscale exposure effects affecting stochastic failures. We apply acceleration to the stochastic model and perform computational inspection and classification of hot spots on a large layout area. The agreement between predicted probabilities of occurrence and observed defect frequencies are given for both line and space hot spots. We then perform computational inspection upon a virtual process and select hot spot locations and affect repairs. The actual mask is then fabricated, real wafers are exposed, processed, inspected and measured to compare the predicted reductions in defect probabilities with actual measured defect frequencies on wafer.
As the semiconductor industry progresses towards the 2nm logic technology node in pursuit of improved chip performance and density, the demand for minimum pitch scaling in the back-end-of-line (BEOL) interconnect becomes crucial. Imec N3 logic design rules defined a minimum Metal 2 (M2) layer pitch of 30 nm, representing 2nm technology nodes. To further enhance semiconductor integrated circuit performance, attention is shifting towards advanced mask materials for current 0.33 NA EUV scanners. Low-n masks have been shown to improve extreme ultraviolet (EUV) imaging performance in terms of Local-CDU (LCDU), reduced mask 3D effects and improved optical contrast compared to a Tabased mask. In our study, we observed notable enhancements in optical contrast for real logic designs using a low-n mask. Our findings demonstrate an impressive LCDU of 5.5 nm and CGDU of 5.5 nm for Place’n’Route (PnR) structures at a pitch of 32. Furthermore, we successfully printed tip-to-tip (T2T) features as small as 20 nm on the wafer for regular tip-to-tip structures that didn’t get any Optical proximity Correction (OPC). These advancements mark significant progress towards manufacturability and developing a holistic patterning approach for random logic metal with EUV.
With the increasing complexity of semiconductor manufacturing processes, from early R&D through ramp and high-volume manufacturing (HVM), a myriad of data analysis solutions are required for fast and actionable decisions in a fab. In our previous work, we used the SEM metrology capabilities of aiSIGHT to perform shape analysis and defect detection of contact holes and pillars in tight-pitch DRAM structures such as storage node landing pad arrays (SNLP) to gain insights on process variability. This paper focuses on a different type of metrology application, extracting unbiased roughness from mask and wafer SEM images, such as unbiased line edge roughness (LER) and line width roughness (LWR), along with defect detection.
To maintain lithographic pitch scaling, extreme ultraviolet (EUV) processes have been adopted in high-volume manufacturing (HVM) for today’s advanced logic and memory devices. Among various defect sources, stochastic patterning defects are one of the most important yield detractors for EUV processes. In this work, we will limit our scope to patterning defects arising out of lithography. In the past, it has been shown that the patterning defect process window is often limited by stochastic hotspots. These hotspots have very low failure probabilities in a well-optimized process, and hence their detection necessitates large area sensitive defect inspection, such as with a broadband plasma (BBP) optical defect inspection system. It has also been shown that systematic issues in design can be exacerbated by stochastic variations. Hence, it is critical to discover these hotspots and study their variability with massive SEM metrology. Such analyses can uncover systematic trends, which can then be corrected and monitored. In this work, we discover hotspots using broadband plasma (BBP) optical inspection and study their variability using KLA’s aiSIGHT™ pattern-centric defect and metrology software solution for automatic defect classification and SEM metrology measurements. We also demonstrate the need for fast and rigorous 3D probabilistic stochastic defect detection on design as a continuation of this work.
Edge placement error (EPE) has become a critically important metric in semiconductor manufacturing. EPE quantifies the difference between the designed and printed layout of devices, coupling overlay and critical dimension (CD) of different litho layers. EPE consists of global and local components and can manifest itself between different physical layers of a device (e.g., via, metal) or within a single layer (primarily relevant for multi-patterning). This paper will study the simplest case of a single layer using an N10 litho-etch-litho-etch (LELE) metal layer patterning and will mainly cover global EPE. Monitoring and control of EPE will enable the stability of integrated circuit devices in advanced technology nodes. Inline EPE prediction in the process control loop at previous litho and etch steps enables early wafer status diagnosis and process disposition, which will improve process margin and wafer yield. Overlay and CD are essential inputs for EPE monitoring, prediction and control. Direct measurement of EPE on the device provides a reference value for an EPE model with overlay and CD measured on special targets. KLA’s pattern-centric solutions provide unique and accurate functionality in EPE metrology by analyzing SEM images on devices or targets in combination with the chip design. In this paper, we conduct experiments for EPE modeling and perform reference analysis using KLA’s pattern-centric solutions, targeting a higher pass rate of e-test, lower defectivity and targeted SEM inspection. KLA’s pattern-centric solutions are applied to e-beam images and provide die-to-database analysis by extracting measurements. The resultant EPE analysis can provide a higher correlation between electrical test data and targeted hotspot inspection, and can also be used to build the EPE model, for example, using e-overlay or CD targets. Overall, the results of these studies show good agreement with EPE model predictions and measured EPE by KLA’s pattern-centric solutions on device structures.
To continue the future of dynamic random-access memory (DRAM) manufacturing with EUV and high NA EUV, alternative techniques for nanofabrication are required to reduce the cost and simplify the processes. In this report, we present the results of the development of a single mask solution with 0.33NA EUV lithography for two important layers, bit-line-periphery (BLP) and storage-node-landing-pad (SNLP), in DRAM manufacturing. The methodology has been established for our examination and assessment of the process window (PW) of the critical dimensions (CD) and the defectivity of the SNLP and BLP layers. Based on this methodology, a pitch 34nm DRAM has been optimized with the spin-on metal oxide resist (MOR) and dark field of a binary mask. We obtained the large overlapping PW of CDs (with a depth of focus of 119nm and an exposure latitude of 25% at a dose-to-size of 89.4mJ cm-2) in the free-defect ranges (20mJ cm-2). We achieved around ~22% dose reduction using the same processes with spin-on MOR applied to the new design of a low-n mask. We observed a pitch of 32nm SNLP and BLP with a single mask layer due to a low-n mask. Additionally, the process window discovery (PWD) methodology for defect inspection in the large area of SNLP and BLP shows good progress which can be applied for optimized conditions. We believe that our results show the resolution limit of 0.33NA lithography for the single mask print SNLP-BLP and 0.55NA EUV is needed for the next generations of DRAM.
Background: Natural physical phenomena occurring at length scales of a few nm produces variation in many aspects of the EUV photoresist relief image: edge roughness, width roughness, feature-tofeature variability, etc. 1,2,3,4. But the most damaging of these variations are stochastic or probabilistic printing failures 5, 6. Stochastic or probabilistic failures are highly random with respect to count and location and occur on wafers at spectra of unknown frequencies. Examples of these are space bridging, line breaking, missing and merging holes. Each has potential to damage or destroy the device, reducing yield 6, 10. Each has potential to damage or destroy the device, reducing yield 6, 10. The phenomena likely originates during exposure where quantized light and matter interact1 . EUV lithography is especially problematic since the uncertainty of energy absorbed by a volume of resist is much greater at 13.5 nm vs. 248 nm and 193 nm. Methods: In this paper, we use highly accelerated rigorous 3D probabilistic computational lithography and inspection to scan an entire EUV advanced node layout, predicting the location, type and probability of stochastic printing failures.
This paper presents a feasibility study on patterning the critical layers of Bit-Line Periphery (BLP) and Storage Node Landing Pad (SNLP) for advanced 10nm node DRAM with sub-40nm pitch using a single EUV patterning. Source Mask Optimization (SMO) and aerial image-based Optical Proximity Correction (OPC) were initially conducted to classify image data and identify potential weak points of the primary patterning mask. A secondary patterning mask was then produced based on the resist model and design split using the obtained data on the primary mask to address these issues. Results obtained through PV-band and intensity analysis of each area in simulation, as well as ADI and AEI (After Etch Inspection) using photoresists with 2 kinds of different tones (PTD CAR and Spin-on MOR PR), demonstrated the feasibility of patterning BLP and SNLP with a single EUV mask. Additionally, Process Window Discovery (PWD) wafers were fabricated to analyze and review process margins and potential weak points through KLA inspection for systematic patterning defectivity. Furthermore, our experiments confirmed that the performance of EUV patterning with DRAM BLP/SNLP layer can be expected to improve by reducing the dose (in mJ/cm2) by approximately 30% using a secondary mask by retarget bias split and resist model OPC.
Variability control has been a key enabler for achieving continuing technology shrinks in both logic as well as DRAM. With ever-tightening requirements, simple one-dimensional metrology and control aspects, i.e. separate variability control for CD and overlay, are no longer adequate [1]. To improve on this approach, simultaneous control of more than one parameter has been discussed to minimize the parametric yield impact. One such example is to improve edge placement error (EPE), a metric where overlay and CD metrology are combined [1]. In this work, we will revisit the EPE concept from the perspective of using established methodologies used in yield modeling. Rather than starting with a litho-centric approach, we cast the problem as a parametric yield loss mechanism driven by patterning parameters. In contrast to the widely disseminated EPE budget that originates from a patterning process-centric view, we introduce a modified analysis framework. The development of the approach discussed in this work starts with well-known yield engineering approaches rooted in defectivity modeling/statistics. It then proceeds towards quantifying and thus allowing a statistically sound quantification and thus prioritization of patterning (i.e. litho or post etch) improvements based on their impact on the yield loss Pareto. In doing so, the new formalism sheds light on what aspects of the EPE distribution most prominently affects yield loss. It also reveals that the ratio of potentially failing instances with a die and the max number of fails tolerable before the die fails plays a role in formulating any kind of budget approach. When putting our concepts to the test we discovered that there is yet another significant contributor affecting the acceptable variation range. We find that the “rigid structure approach”, an inherent assumption in any budget breakdown, and feature-to-feature interactions drive a significant reduction of the available processing tolerances. We attribute this mechanism to the 3D aspects of the patterning process and present a model that can handle the interactions. Finally, we discuss our approach to addressing the fact that process variability happens on length scales that cover several orders of magnitude. We developed a physical budget breakdown that attempts to optimize the tradeoff between sample size and the ability to capture variability over this wide range of length scales. We will postpone our discussion on other sampling-related topics. The question of how one obtains all required metrology data on one wafer in a manufacturing environment will be addressed in a future publication.
As the industry continues to scale DRAM cell size, EUV lithography techniques have been considered in one or multiple steps. We have explored a single mask solution to pattern the bit-line-periphery (BLP) and the storage node landing pad (SNLP). Normally, for such varied types of structures as honeycomb arrays, SWD, S/A and Core, multiple masks are required. In this paper, we have explored a single EUV mask approach. First, a freeform EUV light source (in the source mask optimization, or SMO, process) was generated targeting a 36nm pitch honeycomb array and BLP structures. Then, curvilinear optical proximity correction (OPC) was applied to the target design (as shown in Figure 1) such that the performance meets qualified process window variation bands (PVBs) with proper curvilinear mask rule check (MRC). It is important to note that only an optical model was used for SMO and OPC without a resist model in this task. For the wafer process, we have used a dark field mask and metal oxide resist (MOR) photoresist and negative tone development (NTD). This was followed by transferring the pattern into a suitable hardmask for optical defect characterization using the KLA broadband plasma (BBP) 29xx tool as shown in Figure 2. Process window characterization was done to discover a unified defect-free window for both honeycomb array and BLP structures.
The new generation of 10nm node DRAM devices have now adopted EUV based patterning techniques. With further shrink in design rules, single exposure EUV processes will be pushed further using advanced photoresists and new mask types. However, in absence of high NA EUV lithography ready for high volume manufacturing (HVM) until at least 2025, acceptable local CD (critical dimensions) uniformity and yielding process windows at low exposure dose are a challenge for single exposure EUV. Further, for EUV implementation in sub-32nm pitch DRAM capacitator patterning applications, multi-patterning techniques must be explored. In this paper, EUV based double-patterning techniques have been demonstrated to pattern honeycomb array contact holes and pillars. The processing utilizes two EUV masks, using simple angled line space patterns. We have explored two different types of double patterning options: litho-freeze-litho-etch (LFLE) to pattern contact holes and litho-etch-lithoetch (LELE) to pattern pillars. In the absence of high NA EUV, these processing techniques are useful to pattern tight pitch (e.g., 32nm) contact holes/pillars for newer generations of DRAM devices. Another key objective of this paper is to present a set of metrology characterization methods to enable proper process optimizations.
As we strive toward smaller and smaller pitches and new 3D constructs to enable device scaling, thorough defect characterization at wafer scale is essential during the early phases of process optimization. Often CD (critical dimension) variations and roughness lead to high SEM (scanning electron microscope) inspection noise. It is important to suppress this noise and increase DOI (defect of interest) SNR (signal-to-noise ratio) for better detection efficiency while maintaining high speed for meaningful wafer coverage. In this work, we describe experiments and show characterization results for capturing EUV (extreme ultraviolet) stochastic defects across various test structures of 28nm pitch devices that have been patterned using single exposure 0.33NA EUV lithography. We have used KLA eSL10TM for SEM inspection and analysis. The tool can also be used for high resolution and high-speed metrology, providing quick feedback on observed defect signatures and further root cause analysis.
As we strive toward smaller and smaller pitches to enable device scaling, thorough defect characterization at wafer scale continues its importance during the early phases of process optimization. In this paper, we describe experiments and show characterization results for capturing stochastic defects across various test structures of 28 nm pitch devices that have been patterned using single exposure EUV lithography. The objective of this work is to quantify detection sensitivity of critical defect types on multiple test structures, and study wafer and die level signatures for some of the types. We will employ various, complementary optical and e-beam inspection and review techniques. Further, new methods to increase sensitivity of optical inspection after litho are also discussed.
In this paper, we will investigate defect modes and pattern variations for EUV (extreme ultra-violet lithography) double pattering scheme using self-aligned litho-etch-litho-etch process on final pitch 28nm test structures. As we continuously shrink device sizes towards aggressive pitches, the industry is moving towards adopting double pattering using EUV. Although we continue to push limits of 0.33NA EUV in terms of pitch and CD (critical dimensions) with novel resists and processes, stochastic defects pose greater challenge at pitches below 40 nm [1]. One of the ways to circumvent this problem is to use a multi-patterning scheme with relaxed design rule. Self-aligned litho-etch-litho-etch (SALELE) is one such scheme for early BEOL (back end of line) layers. The benefit of this patterning approach is that no dummy metal is added and blocks are needed only at tight tip-to-tip definitions, which can help to reduce parasitic capacitance. In this paper we will employ SEM inspection techniques to understand pattern variabilities, after initial optical inspection was done to discover different defect modes. We show that with analysis of SEM images we can get further insight on process variations.
As extreme ultra-violet (EUV) lithography moves into high volume manufacturing (HVM) for several critical layers for the N5 node, there is a need to develop a comprehensive strategy for mask re-qualification in the fab to mitigate contamination risks. The introduction of additional particle sources due to the scanner vacuum system and potential growth of film or particle deposition on the reticle, in combination with pellicle uncertainty, pose unique inspection challenges for EUV reticle defectivity compared to 193i reticles. EUV reticles are typically inspected with optical reticle inspection tools at outgoing quality control during their manufacture. Optical reticle inpsection tools are also traditionally used in the IC fab for incoming reticle qualification and periodic reticle re-qualification during production. However, to reduce material at risk in the IC fab there is a need for alternate inspection methodologies based on inspection of printed wafers. In addition, potential new defect mechanisms, such as those associated with the multi-layer mask of the EUV reticle, are driving fabs to re-qualify reticles in production using new methods that involve printed wafer inspection. The printed wafer inspection methodology is referred to as “reticle print check” or simply “print check”. In this paper we will describe the print check flow and show results from new developments in this methodology improving the capture of mask defects on wafer.
Stochastics defect detection has been a topic of intense study by the extreme ultraviolet (EUV) patterning fraternity [1]. A large part of this initial feasibility work has been performed using electron microscope-based systems [1,2]. A limited sample area is imaged using electron microscopes and images are analyzed using offline analysis techniques [1,2]. However, to accurately quantify the stochastics failure rate, the entire area of interest needs to be inspected. Given such large area inspection requirements, automated and high throughput solutions are the need of the hour to enable stochastics quantification in HVM (high volume manufacturing). This paper demonstrates Broadband Plasma optical wafer inspection capability to capture two key defects on EUV layers a) missing contact in contact hole array patterns b) line breaks in line- space pattern.
KEYWORDS: Semiconducting wafers, Critical dimension metrology, Metrology, Modulation, Inspection, Copper, Chemical mechanical planarization, Defect inspection, Extreme ultraviolet lithography, Back end of line
With continuous scaling and increased design and process complexity, there is an increasing need for semiconductor manufacturing process control. This need calls for not only advanced methods and more capable tools, but also additional intra-wafer and across-lot sampling in order to capture process variations and/or changes in process signatures. In this paper we will demonstrate high speed full wafer metrology use cases from the KLA CIRCL™ platform. The CIRCL platform is typically used for very high throughput inline macro defect inspection. Here we demonstrate that this tool can also be used for certain types of metrology applications. In this paper, we will investigate metrology opportunities with full wafer coverage for critical process parameters on two test vehicles: (1) a 32nm pitch regular line-and-space defect vehicle patterned with single exposure EUV and (2) an iN7 BEOL integration test vehicle, also patterned with single exposure EUV.
With the adoption of extreme ultraviolet (EUV) lithography in high volume manufacturing (HVM) to enable the sub-7nm scaling roadmap, defect characterization brings new challenges and learnings. Traditional approaches to process window discovery (PWD) methodology developed2,3,4 using broadband plasma optical inspection also hold in the realm of EUV lithography. Although there is substantial depth of focus for regular patterns, focus continues to be an important modulation parameter for logic patterns. Dose is an important modulation parameter especially due to stochastic defects.1 Further, overlay is another important parameter when it comes to hybrid integration schemes such as self-aligned quadruple patterning (SAQP) and EUV block patterning, for example, in BEOL layers. In this paper, we will discuss PWD results on a foundry N5 equivalent M2 layer, studying both SAQP and block integration with direct EUV patterning. We also demonstrate the impact of EUV stochastics to the overall process window and develop useful analysis methodologies.
As Extreme UltraViolet (EUV) lithography nears high volume manufacturing (HVM) adoption to enable the sub-7nm scaling roadmap, characterizing and monitoring defects that print at wafer level are of critical importance to yield. This is especially true for defects coming from the EUV mask, such as multi-layer defects, added particles or growth on mask, and for defects coming from the pattern formation process itself, also referred to as stochastic printing defects. A “Print Check” solution has been previously described.1 This technique uses full-wafer patterned optical inspection to monitor mask defects that print on the wafer. In this paper we focus on developing metrology solutions for stochastic printing defects, which are random local variations that occur between structures that should, in principle, print identically, but actually occur at significant frequencies with current state-of-the-art processes. Specifically, we discuss the importance of monitoring these defects using broadband plasma optical inspection and e-beam defect review systems. We show extensive characterizations of defects on line space patterns down to a pitch of 36nm, on contact holes at a pitch of 48nm and on logic blocks in a foundry equivalent N5 test vehicle. Analysis methods based on CD SEM and review SEM images have been described.
As the Extreme Ultraviolet (EUV) lithography ecosystem is being actively mapped out to enable sub-7nm
design rule devices, there is an immediate and imperative need to identify the EUV reticle (mask) inspection
methodologies [1]. The introduction of additional particle sources due to the vacuum system and potential growth of
haze defects or other film or particle depositions on the reticle, in combination with pellicle uncertainty pose unique
inspection challenges when compared to 193i reticles.
EUV reticles are typically inspected with optical reticle-inspection tools. However, if there is a pellicle on the
EUV mask which is non-transmissive to the optical wavelengths used in the reticle inspection tools, then there is a need
for alternative inspection methodologies based on inspection of printed wafers. In addition, due to the potential new
defect mechanisms associated with the EUV reticles, fabs are looking for additional methods to re-qualify reticles in
production using printed wafer inspections. The printed wafer inspection methodology is referred to as “Reticle Print
Verification” or “Reticle Print Check.” This paper discusses these alternative inspection methodologies that are being
developed in collaboration with imec using an advanced broadband plasma (BBP) patterned wafer optical inspection
(KLA-Tencor 3905) and e-beam review systems (KLA-Tencor eDR7280).
The performance requirements of advanced semiconductor technology nodes necessitate the use of
complex processing methods that push patterning beyond the physical limits of DUV immersion
lithography (ArFi). Specifically, aggressive process window and yield specifications put tight requirements
on scanner imaging performance.
Accurate identification of process windows can be accomplished using KLA-Tencor’s fixed focus offset
conditions and Process window Discovery (PWD) methodology[1]. The PWD methodology makes use of a
modulated wafer layout to enable inspection comparing nominal to modulated conditions. KLA-Tencor’s
Broadband plasma (BBP) inspection technology is used to compare the nominal conditions to each
experimental condition and to identify systematic defects. The identification of systematic defects is
enabled by the PWD method by first discovering potential patterns of interest and then generating
NanopointTM care areas around every occurrence of the patterns of interest. This allows identification of
critical systematic structures that may have the same design intent but do not repeat in the same X,Y
locations within a device. This approach maximizes the inspection sensitivity on each structure type,
accurately identifies the edge of the process window in focus and dose, and enables study of the sensitivity
of fixes process offsets (such as light source bandwidth).
In this study, a tunable DUV light source bandwidth technique and the PWD methodology are used to
study the light source E95 bandwidth impact on Metal layer features from an imec 10 nm node logic-type
test vehicle.
Analysis of hotspots is becoming more and more critical as we scale from node to node. To define true process windows at sub-14 nm technology nodes, often defect inspections are being included to weed out design weak spots (often referred to as hotspots). Defect inspection sub 28 nm nodes is a two pass process. Defect locations identified by optical inspection tools need to be reviewed by review-SEM’s to understand exactly which feature is failing in the region flagged by the optical tool. The images grabbed by the review-SEM tool are used for classification but rarely for quantification. The goal of this paper is to see if the thousands of review-SEM images which are existing can be used for quantification and further analysis. More specifically we address the SEM quantification problem with connected component analysis.
This manuscript shows the relationship between defectivity of a typical chemo-epitaxy sequence and the DSA-specific materials, namely the mat, the brush and the block co-polymer. We demonstrate that the density of assembly defects in a line-space DSA flow, namely the dislocations and 1-period bridges have a direct correlation to certain parameters in the synthesis sequence of these materials. The primary focus of this manuscript is on identifying, controlling and reproducing the defects-critical parameters in the block co-polymer synthesis process for a stable and low defect performance of DSA flows.
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