For 45 nm node and beyond, the alternating phase-shift mask (alt. PSM), one of the most expected resolution
enhancement technologies (RET) because of its high image contrast and small mask error enhancement factor (MEEF),
and the binary mask (BIM) attract attention. Reducing CD and registration errors and defect are their critical issues. As
the solution, the new blank for alt. PSM and BIM is developed. The top film of new blank is thin Cr, and the antireflection
film and shielding film composed of MoSi are deposited under the Cr film.
The mask CD performance is evaluated for through pitch, CD linearity, CD uniformity, global loading, resolution and
pattern fidelity, and the blank performance is evaluated for optical density, reflectivity, sheet resistance, flatness and
defect level. It is found that the performance of new blank is equal to or better than that of conventional blank in all
items. The mask CD performance shows significant improvement.
The lithography performance of new blank is confirmed by wafer printing and AIMS measurement. The full dry type
alt. PSM has been used as test plate, and the test results show that new blank can almost meet the specifications of pi-0
CD difference, CD uniformity and process margin for 45 nm node. Additionally, the new blank shows the better pattern
fidelity than that of conventional blank on wafer. AIMS results are almost same as wafer results except for the
narrowest pattern. Considering the result above, this new blank can reduce the mask error factors of alt. PSM and BIM
for 45 nm node and beyond.
We propose a new criterion for mask birefringence in polarized illumination. Mask birefringence is one of the
critical properties of polarized illumination, because the illumination polarization is disturbed by the birefringence of a
mask substrate. From this point of view, the allowable mask birefringence has already been analyzed. In these analyses,
only the absolute values of birefringence have been specified. As has been pointed out, the mask is a rotation retarder
for the polarized illumination. Therefore, the angle of the fast axis of mask birefringence also affects the state of
polarization.
The new criterion of mask birefringence which we propose here adopts the angle of fast axis as well as the
absolute value of birefringence. This new criterion correlates well with the printed critical dimensions (CDs). To
demonstrate this, printed CDs were calculated as a function of birefringence. A lithography simulator was used to verify
the fit of the new criterion. In this simulation, experimentally measured absolute values of birefringence and the angle
of fast axis were used. The simulation showed that there was poor correlation between printed CDs and the absolute
values of birefringence. On the other hand, the new criterion exhibited a good correlation with the printed CDs. This
difference is attributed to the effect of the angle of fast axis.
This paper presents the impact of hyper-NA (NA > 1) lithography on the specification of mask critical-dimension (CD) uniformity. In order to realize the hyper-NA lithography, it is needed to adopt new technologies such as a liquid-immersion setup and polarized light illuminator. In the immersion lithography, it has been shown that the mask CD tolerance can be relaxed if NA is increased. This relaxation originates from the increase of the exposure-latitude (EL) in defocus conditions. As has also been reported, polarized light imaging enhances the EL of line-and-space patterns. This indicates that the application of polarized light imaging may enable us to relax the mask CD tolerance. In this paper, the mask CD relaxation will be discussed based on lithography simulations. In addition, the influences of mask birefringence and state of polarization in illuminator on the wafer CD will be discussed. Quartz substrate used as a mask blank can act as a rotation retarder, because of the presence of intrinsic stress induced in manufacturing processes. Therefore, the state of polarization of mask-transmitted light is disturbed. As a result, wafer CD is affected both by the mask birefringence and state of polarization in illuminator; hence, specification of mask CD uniformity (CDU) is also influenced. In this paper, the specification of mask CDU will be discussed by taking the effect of the impact of state of polarization in illuminator and mask birefringence into account. These results accelerate the practical use of hyper-NA lithography in 45-nm node.
For the purpose of finding feasible dual-BARC (Bottom Anti-Reflective Coating) parameters for immersion lithography that do not depend on the polarization of light, illumination conditions and pattern sizes and pitches, comprehensive optimizations of the dual-BARC parameters were performed. A computational code was developed that performs automatic and comprehensive optimizations of dual-BARC parameters under any kind of conditions. Margins of dual-BARC parameters, which assure the substrate reflectance to be lower than a desired value, were also estimated by using the code. Dual-BARC parameters to minimize the substrate reflectance were successfully obtained for the BARC formed on a silicon oxide and nitride layer for cases of NA being 1.0, 1.1, 1.2 and 1.3 to 1.4. The thickness of the silicon oxide and nitride layer was varied from 10 to 200 nm. It was found that the dual-BARC concept works up to NA = 1.1 and 1.4 for the BARC on a silicon oxide and a silicon nitride layer, respectively, although for the case of the dual BARC on a silicon oxide layer, the range of the thickness of the oxide layer where the dual-BARC concept works is limited. In addition, for both of the cases of the dual BARC on silicon oxide and nitride, it was calculated that the top-layer of the dual BARC has to be extremely thin. Feasibility of using a layer structure consisting of a planarization and hardmask layer as a reflection-control structure was also examined. This showed that this concept can work up to NA = 1.2 and 1.4 for the case on silicon oxide and nitride, respectively. Finally, a routine to optimize graded-BARC structure was successfully implemented into our computational code. By using the routine, advantages of the graded-BARC concept over the dual-BARC concept in terms of suppressing substrate reflectance were demonstrated.
For an ultra-high numerical aperture (NA), such as that exceeding 0.9, the p-polarized component of light that has passed through a region at the limit of the NA of a high-NA lithography tool, degrades contrast because of the so-called vector imaging effect, and is therefore detrimental to the formation of optical images. Polarized illumination removes the effect of the p-polarized light component and provides illumination light composed of s-polarized light. The higher the NA, the greater are the benefits of polarized illumination. Therefore, in lithography at the 45-nm node and below, polarized illumination is viewed as an indispensable technology. We explore the applicability of polarized illumination to device manufacturing processes at the 45-nm node and beyond, with a focus on the utilization of azimuthally polarized illumination, which enables one mask exposure. The data used in this research were obtained through imaging simulations and experiments using a dry lithography tool equipped with a 0.92-NA projection lens. In imaging simulations using a lithography simulator, the application of azimuthally polarized illumination improved image contrast in resists by approximately 20% for half pitch (HP) 65-nm dense patterns. As a result, device patterns showed enhanced robustness with respect to exposure dose error; extended process windows; and reduced mask error enhancement factor (MEEF), line edge roughness (LER), and line end shortening (LES). This paper examines the results of experiments conducted using imaging simulations and lithography tools on other product device like patterns (besides special patterns in which benefits can clearly be expected, including dense (L/S) patterns), and reports the results.
Dry-etch two-dimensional (2D) model functions have been investigated via 2D SEM image analyses. To evaluate dry-etch bias with respect to its 2D geometry, critical 2D pattern shapes of pre- and post-dry-etch process were compared. From the geometrical evaluation results we have confirmed that dry-etch biases can be expressed by a linear function of 2D pattern/space densities, for which integration should be taken only inside of nearest-neighbor pattern edges. It is guessed that those specific densities are required for estimating the thickness of passivation polymer films upon etching trench sidewall, which is assumed to be a critical factor for etch bias variations. We have obtained good correlations between etch bias and inside-edge pattern/space density; correlation coefficients of 0.95 for SiO2 trench etching process and 0.94 for Si trench etching process have been obtained, respectively. Optimum kernel radii of these processes were about 600 nm - 800 nm in our experiment. These distances would indicate the scope of micro-loading effect. If device pattern complexities come to these sizes, 2D pattern correction by 2D model function should be required for dry-etch biases instead of current rule-based correction.
This paper presents the first results on mask critical-dimension (CD) specifications for the hyper-numerical aperture (hyper-NA) lithography. The mask CD specifications have been derived from experimental results applying the immersion lithography with NA being 0.85. The experiment has been performed for a hole pattern corresponding to the 65-nm node with NA = 0.75 or 0.85. From this experiment, it was found that the higher-NA condition (NA = 0.85)
makes the mask CD tolerance being more than doubled as compared to that under the lower-NA condition of NA = 0.75 while retaining the depth-of-focus (DOF) margin. This relaxation in the CD tolerance is attributable to the enlargement of DOF in the immersion lithography where the DOF becomes more than n times larger than that with the dry
lithography under the same resolution limit (n: refractive index of immersion fluid). Analyses of the mask CD tolerance have been performed by applying a newly-developed method, that enables a quantitative analysis of mask CD error and DOF margin. In addition, the mask CD error margin for the 45-nm node have also been estimated by performing a lithography simulation under conditions with NA = 1.07 and 1.20. From this simulation, it was predicted that for the
case when NA = 1.07, the mask CD error margin requires specifications on mask that are almost unachievable if one concerns the status of current mask manufacture processes together with the forecast on the processes given in the ITRS 2004 roadmap. On the other hand, the simulation predicted that the higher-NA condition (NA = 1.20) with the immersion imaging realizes a relaxation in the mask CD tolerance, leading to realistic specifications on mask. Therefore, this strategy realizes a breakthrough to avoid the "mask crises".
Parameter optimization is a key issue to develop low-k1 lithography processes, in which the number of control and error factors has been increasing. This holds especially true for alternating phase-shifting mask (alt-PSM) techniques; i.e., for this technique, not only exposure conditions but also mask structures should be optimized under various error factors (or noise factors), such as defocus, dose fluctuations, lens aberrations, mask making errors and so on. This paper describes a novel method of performing such optimization, which is developed based on a method of design of experiments (DOEs). Stabilities of target performance for various combinations of parameters are simulated by varying noise factor levels which are assigned to an orthogonal array. Optimum values of parameters are determined so as to maximize the stabilities of target performance.
This method is applied to a 45-nm node alt-PSM (alternating phase-shifting mask) technique. Optical conditions, such as NA (numerical aperture) and σ-value, and mask structures, such as trench depth and undercut size, are optimized under various noise factors by applying our method for optimization. As a result, high stability of critical dimension (CD) is obtained together with sufficient suppression of image placement errors. The optimized result is further verified by statistic calculations. Finally, we conclude that our method is a very powerful tool to simultaneously optimize lithographic conditions for low-k1 lithography processes.
Parameter optimization is a key issue to develop low-k1 lithography processes, in which the number of error factors and that of critical patterns have been increasing. In order to attain a target performance of integrated circuits under numerous error factors (or noise factors), this paper describes a novel method to optimize various parameters simultaneously. The parameters include not only those related to exposure conditions such as NA, sigma and etc, but also include those related to layout restrictions for various patterns. The optimization method we applied is based on the Taguchi method for robust design experiments, which uses orthogonal arrays with a single criterion, which is called “signal-to-noise (SN) ratio”, for optimization. The optimization is performed so as to maximize the SN ratio for a pattern critical-dimension (CD) or the SN ratio for an operating window such as the open-to-short operating window of electric connections. Two cases of optimization are reported in this article, one for an intermediate metal layer in a 45 nm-node device, and the other for a via-hole layer connected to the metal layer. Any type of noise factors and critical patterns could be taken into account and an optimum set of parameters could be determined quickly and simultaneously by applying the method. The results demonstrate that this global optimization method is a very powerful tool to optimize multiple parameters in low-k1 lithography processes.
We have developed a new pattern correction method to improve the uniformity of gate width and thus transistor characteristics. It is well known that the width of the gate pattern as exposed with an alternating phase shift mask (alt-PSM) varies along the gate width direction, owing to the optical-intensity maxima within the phase shifter regions on both sides of the gate. Since the positions of the maxima depend on the shifter height, the pattern pitch and the illumination conditions (σ and NA), the degree of distortion of the gate length also depends on these factors. We have found that the optimal segment size for optical proximity correction (OPC) of gate distortion also depends on the above factors and should be determined by simulation prior to OPC. From our simulations, shorter segments do not necessarily lead to higher correction accuracy, and the optimal size is strongly related to the degree of distortion. Based on these observations, we propose a novel correction method, in which the look-up table of optimal segment size as a function of shifter height and pattern pitch is referred to in the model-based OPC flow. The advantage of the method has been shown by comparing the correction results to those from the ordinary model-based method, with the latter focusing on the line-end regions where the distortion effects are most remarkable.
Line end shortening (LES) effects and their corrections for ArF attenuated phase shift mask (PSM) technology toward 65 nm node, both in photomask and wafer processes, have been investigated. From critical dimension (CD) measurements on photomasks, it was found that line end distance and line width are the relevant factors for line end deviations on clear field and dark field types, respectively. We confirmed that these mask errors can significantly be reduced by rule base process proximity effect correction (PPC). Subsequently we analyzed resist LES on wafers and found that resist LES shows a down slope in case line end distance is less than 200 nm. We also assessed mask error enhancement factor (MEEF) around line end. Line end MEEF for a clear field mask indicates 3.4 when line end distance is 80 nm. By examining the relation between line end rounding on photomask and corresponding resist LES, we confirmed line end area loss on photomask surely induced larger resist LES. Lastly, we have evaluated a new optical proximity effect correction (OPC) approach in which correction for mask errors is separated from wafer OPC calculation. It is confirmed that new integrated OPC is promising for improving LES.
Because of the mask error enhancement factor (MEEF), iso-dense biases of mask patterns are amplified when the image is transferred to a wafer. A slight critical-dimension (CD) difference between an OPC test mask and an OPCed mask may cause a significant OPC error on the wafer. The impact of the mask CD error on OPC accuracy has never been evaluated, however, to evaluate the impact of the inter-mask CD error (IMCDE), we measured the CD errors of various line-and-space patterns on attenuated phase-shifting masks for ArF exposure. We investigated the effect of IMCDE and the iso-dense biases of test-mask patterns on OPC accuracy. We found that a degree of IMCDE is tolerable in attenuated phase-shifting ArF masks. This tolerable degree of IMCDE is useful to gauge the effectiveness of the OPC, with an eye to developing a lithographic process for semiconductor production. Furthermore, based on experimental results showing that a wafer CD is controllable when scanner conditions such as numerical aperture (NA) and partial coherence factor (sigma) are optimized, a new mask-matching method to compensate for the IMCDE is proposed.
An alternative phase shift mask (alt-PSM) is a promising device for extending optical lithography to finer design rules. There have been few reports, however, on the mask's ability to identify phase defects. We report here an alt-PSM of a single-trench type with undercut for ArF exposure, with programmed phase defects used to evaluate defect printability by measuring aerial images with a Zeiss MSM193 measuring system. The experimental results are simulated using the TEMPEST program. First, a critical comparison of the simulation and the experiment is conducted. The actual measured topographies of quartz defects are used in the simulation. Moreover, a general simulation study on defect printability using an alt-PSM for ArF exposure is conducted. The defect dimensions, which produce critical CD errors, are determined by simulation that takes into account the full 3-dimensional structure of phase defects as well as a simplified structure. The critical dimensions of an isolated bump defect identified by the alt-PSM of a single-trench type with undercut for ArF exposure are 300 nm in bottom dimension and 74 degrees in height (phase) for the real shape, where the depth of wet-etching is 100 nm and the CD error limit is +/- 5 percent.
An alternative phase shift mask (alt-PSM) is a promising device for extending optical lithography to finer design rules. There have been few reports, however, on the mask's ability to identify phase defects. We report here an alt-PSM of a dual-trench type for KrF exposure, with programmed quartz defects used to evaluate defect printability by measuring aerial images with a Zeiss MSM100 measuring system. The experimental results are simulated using the TEMPEST program. First, a critical comparison of the simulation and the experiment is conducted. The actual measured topography of quartz defects are used in the simulation. Moreover, a general simulation study on defect printability using an alt-PSM for ArF exposure is conducted. The defect dimensions, which produce critical CD errors are determined by simulation that takes into account the full 3-dimensional structure of phase defects as well as a simplified structure. The critical dimensions of an isolated defect identified by the alt-PSM of a single-trench type for ArF exposure are 240 nm in bottom diameter and 50 degrees in height (phase) for the cylindrical shape and 240 nm in bottom diameter and 90 degrees in height (phase) for the rotating trapezoidal shape, where the CD error limit is +/- 5%.
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