The mask requirements for 110nm half-node BiCMOS process were analyzed with the goal to meet customer needs at
lower cost and shorter cycle times. The key differentiating features for this technology were high density CMOS libraries
along with high-power Bipolar, LDMOS and DECMOS components. The high voltage components were characterized
by transistors that formed cylindrical junctions. The presence of curved features in the data is particularly detrimental to
the write time on a 50KeV vector mask writer. The mask write times have a direct impact on both mask cost and cycle
time. Design rules also permit rectangular or stretched contacts to allow conductance of high currents. To meet customer
needs but still manage the computational lithography overhead as well as the patterning process performance, this
process was evaluated in terms of computational lithography and photomask co-optimization for the base-line 50KeV
vector and laser mask-writers. Due to the differences in imaging and processing of the different mask writing systems,
comparative analysis of critical dimension (CD) performance both in terms of linearity and pitch was done. Differences
in imaging on silicon due to mask fidelity were also expected and characterized. The required changes in OPC necessary
to switch to the new mask process were analyzed.
KEYWORDS: Photomasks, Deep ultraviolet, Semiconducting wafers, Optical proximity correction, Lithography, Electron beam lithography, Error control coding, Metals, Laser systems engineering, Binary data
One of Cypress’ primary goals for 90-nm generation mask strategy is to control mask costs while not compromising on performance. One key objective is to replace the use of 50-ke V electron beam pattern generation with DUV laser mask lithography where possible. The higher productivity of the DUV laser systems compared to the 50Ke V e-beam platforms offers a unique opportunity for mask cost reduction. Compared to previous i-line generations of laser lithography systems, the DUV laser systems provide significantly improved resolution and pattern fidelity that more closely approaches that of ebeam lithography. We have previously published experimental results demonstrating that the difference in fidelity on the mask between the laser and EB platforms does not always translate to a measurable difference in wafer litho performance or even more importantly to a measurable difference in electrical performance. Through this work, Cypress was able to eliminate the use of 50Ke V ebeam writers for all of their 130nm technology node layers. In some cases the improved performance of the DUV tools was sufficient to replace i-line produced masks where wafer performance was marginal without having to resort to EB lithography. This study addresses the conversion of 50Ke V ebeam layers to DUV laser platform specifically for the critical layers of the Cypress’ 90nm Technology node. EB lithography was originally specified for these layers as a conservative approach in part due to the timing of 90-nm technology development relative to the maturation of the DUV laser mask lithography process. In this study, the electrical performance and wafer yield are evaluated for equivalency in order to take advantage of the lower cost and faster cycletime that use of a ALTA DUV system provides over the 50Ke V VSB systems. In addition, the wafer OPC is not changed between the two mask writing systems in order to allow interchangeable use of the two writing systems if the experimental results indicated no difference in wafer performance.
For logic design, Chrome-less Phase Shift Mask is one of the possible solutions for defining small geometry with low MEF (mask enhancement factor) for the 65nm node. There have been lots of dedicated studies on the PCO (Phase Chrome Off-axis) mask technology and several design approaches have been proposed including grating background, chrome patches (or chrome shield) for applying PCO on line/space and contact pattern. In this paper, we studied the feasibility of grating design for line and contact pattern. The design of the grating pattern was provided from the EM simulation software (TEMPEST) and the aerial image simulation software. AIMS measurements with high NA annular illumination were done. Resist images were taken on designed pattern in different focus. Simulations, AIMS are compared to verify the consistency of the process with wafer printed performance.
Mask CD resolution and uniformity requirements for back end of line (BEOL) layers for the 90nm Technology Node push the capability of I-line mask writers; yet, do not require the capability offered by more expensive 50KeV ebeam mask writers. This suite of mask layers seems to be a perfect match for the capabilities of the DUV mask writing tools, which offer a lower cost option to the 50KeV platforms.
This paper will evaluate both the mask and wafer results from all three platforms of mask writers (50KeV VSB,ETEC Alta 4300TM DUV laser and ETEC Alta 3500TM I-line laser) for a Cypress 90nm node Metal 1 layer, and demonstrate the benefits of the DUV platform with no change to OPC for this layer.
It has long been understood that there is an image fidelity difference between the integrated circuit design pattern and the photomask made from that pattern, largely due to the finite spot size of pattern generators. Furthermore, there are known differences in photomask image fidelity (rounding, jogs, etc.) between e-beam and laser pattern generators. Using a novel technique developed by DuPont Photomasks, Inc. (DPI), actual photomask fidelity has been simulated from design data to produce a more true-to-life representation of the mask. We have performed analytical simulations and printed-wafer measurements on Cypress 100-nm technology designs to determine the differences and effects on optical proximity correction (OPC) of two types of pattern generators: 50 keV e-beam and DUV laser. Both JEOL 9000MV-II+ and ETEC ALTA 4000 images were simulated and saved in GDSII format (“mask-GDSII”). These new mask images were processed through standard lithography simulation software to predict the effects each mask writer has on localized optical proximity effects. Simulations were compared to printed wafer results. A detailed comparison of the accuracy of the mask-GDSII and original design GDSII is performed. Furthermore, comparison of 50 keV e-beam and DUV laser image fidelity is completed, and recommendations are made on how to correct OPC models for each type of photomask generator. Lastly, conclusions are drawn about the use of DUV laser and 50 keV e-beam photomasks.
As we move towards smaller dimensions and denser circuits, Model Based OPC has become a critical and indispensable tool to achieve feature fidelity for random logic and very small bitcell patterns. Model-Based OPC s used to overcome the effects due to the reticle manufacturing process and the photolithography process which are essentially low pass filters, with the objective of returning the intended drawn feature on wafer within acceptable error. In this paper we demonstrate its capabilities and flexibility with the development of a mixed Model-based/Rule based OPC approach that covers all categories of features for the active layer and the heuristics that justify this approach. We discuss along with experimental results the parameterized variations that are possible with Model Based OPC (MBOPC)and the optimization required as a result within the paradigm of a 248nm-lithography process for the 0.13-micron technology. Data and manufacturability issues are discussed that are an important consideration for a feasible MBOPC solution.
It is becoming increasingly clear that semiconductor manufacturers must rise to the challenge of extending optical microlithography beyond what is forecast by the current SIA roadmap. Capabilities must be developed that allow the use of conventional exposure methods beyond their designed capabilities. This is driven in part by the desire to keep up with the predictions of Moore's law. Additional motivation for implementing optical extension methods is provided by the need for workable alternatives in the event that manufacturing capable post-optical lithography is delayed beyond 2003. Major programs are in place at semiconductor manufacturers, development organization, and EDA software providers to continue optical microlithography far past what were once thought to be recognized limits. This paper details efforts undertaken by Motorola to produce functional high density silicon devices with sub-eighth micron transistor gates using DUV microlithography. The preferred enhancement technique discussed here utilizes complementary or dual-exposure trim-mask PSM which incorporates a combined exposure of both Levenson hard shifter and binary trim masks.
It is well known that systematic within-chip dimension (CD) errors can strongly influence product yield and performance, especially in the case of microprocessors. It has been shown that this across chip linewidth variation (ACLV) dominates the CD error budge, and is comprised of multiple systematic and random effects, including substrate reflectivity, reticle CD errors, feature proximity, and lens aberrations. These effects have material, equipment, and process dependencies, with the results being that significant ACLV differences between nominally identical tools/processes can in some cases be observed. We present here a new analysis approach which allows for optimization of exposure/defocus conditions to minimize overall CD errors for a given process. Emphasis is on control of [(mean) + 3 sigma] of CD errors for a given exposure/defocus conditions. Input metrology data is obtained from electrical resistance probing, and data is presented for multiple 248 nm DUV processes and tools with CD ground rules ranging from 180 nm to 140 nm.
The traditional approach for CD and overlay control in lithography has been based upon statistical control of the critical inputs to the lithographic process. This SPC approach has the disadvantage that the process equipment must be taken out of manufacturing whenever a parameter goes out of control, so that the root cause may be diagnosed and addressed. In the case of leading-edge lithography, it is often not trivial to determine the cause of such disturbances, and productivity can be greatly increased if output data is used to dynamically tune the system inputs. We have successfully implemented a fully automated, closed-loop CD and overlay control system in manufacturing for both I-line and DUV lithography. This system features automatic metrology data upload, host control of stepper/track clusters, and utilizes tool-based lot data for manipulation of future lot inputs. CD control to within 1 nm of target and less than 20 nm 3(sigma) lot to lot variability has been demonstrated. Mean overlay errors of less than 50 nm have been realized as well. Process Cpk values were improved in some cases by more than 50% with implementation of the controller.
DUV scanning exposure systems have been steadily gaining market acceptance for the past five years, and soon, all major suppliers will offer 248-nm scanning tools. One of the major reasons for the emergence of this technology has been the purported improvement in critical dimension (CD) uniformity across the scanned field versus what can be realized in a full field stepper. Using high precision electrical resistance CD metrology, we have characterized the across field CD control capability of several DUV scanning tools and DUV steppers. Analysis is carried out through focus for multiple linetypes representing various orientations and nearest-neighbor proximities. Where possible, different NA/(sigma) combinations are examined as well. Surprisingly good full field sub-0.20 micrometers CD control is obtained even for 0.50 NA, and higher NA allows for non zero process latitude at 0.14 micrometers geometries. While it was initially anticipated that 193 nm ArF lithography would be required for 0.18 micrometers technology manufacturing, it has become apparent that 248 nm lithography will be employed for these groundrules, particularly for logic applications with predominantly semi-isolated features.
It is becoming increasingly clear that DUV excimer laser based imaging will be one of the technologies for printing sub-half micron devices. This paper reports the investigation of 0.35 micrometers photolithography process using chemically amplified DUV resists on organic anti- reflective coating (ARC). Production data from the GCA XLS excimer DUV tools with nominal gate width of 0.35 micrometers lines, 0.45 micrometers spaces was studied to demonstrate device production worthiness. This data included electrical yield information for device characterization. Exposure overlay was done by mixing and matching DUV and I-line GCA steppers for critical and non critical levels respectively. Working isolated transistors down to 0.2 micrometers have been demonstrated.
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