Photonic switches promise to have a large impact on future HPC and datacenter networks. However, even if we assume ideal zero-energy photonic switches, we cannot achieve significant system-wide benefits if we do not change the rest of the system architecture. This motivates co-design between emerging photonic switches and the rest of the system in order to adapt the system network to best make use of unique features of photonic switches, as well as tailor photonic switches to better support system-wide trends such as resource disaggregation. In this paper, we discuss the architectural impact of several properties of photonic switches. For each, we provide an overview of what system-level capabilities they enable, how they can be adapted to support ongoing trends, and what other synergistic advancements would produce a better system-wide improvement. In this way, we illustrate the potential benefit of closer collaboration between the photonic and architecture communities.
As bandwidth requirements and integration of photonic components in computing systems increase, the optical micro-ring resonator are becoming an important building block for dense, high-bandwidth interconnects. Ring resonators are small in size and can operate at data rates up to 60Gb/s NRZ,1 making them well-suited for integrating many rings operating at different wavelengths into a single device. These devices are a promising solution for complex interconnected systems, such as chip-to-chip interconnects.2 However, using these rings can be challenging as they are sensitive to fabrication and temperature variations and need constant tuning to lock them to their assigned optical wavelengths.3 This tuning is commonly done by inserting embedded heaters in or above the ring. Existing techniques that tune the rings by the optical power coupled into the rings require extensive characterization and spectrum analysis, or out-of-band signalling, to account for rings drifting across optical channels and fabrication variations. In this work, we use four cascaded micro-rings implemented in a silicon photonic device operating in the C-band. Each ring taps a single wavelength from a bus waveguide. The remaining light in the bus waveguide is then fed into a photodiode, which is used to monitor the tuning of all rings. We show an algorithm that, based only on information about the design of the chip, tunes the rings to the exact desired optical channel. With this algorithm the use of more complex techniques to directly measure a ring's coupled wavelength can be avoided, reducing system complexity.
In this paper, we demonstrate the integration of a SiP switching platform to improve real-world Distributed Denial of Service (DDoS) defense systems. We demonstrate how DDoS mitigation in the optical domain can be transparent to network and application layers, allowing for reconfiguration and tuning. Additionally, we show how optical domain DoS mitigation provides significant cost reduction-with a 1/3 cost reduction-compared to traditional mitigation using electronic counterparts. Our approach is ideal for data-center deployments, and our testbed topology mirrors a standard data center set up.
High bandwidth density silicon photonic interconnects offer the potential to address the massive increase in bandwidth demands for data center traffic and high performance computing. One of the major challenges in realizing silicon photonics transceivers is the integration and packing of photonic ICs (PIC) with electronic ICs (EIC). This paper presents our version one, 2.5D integrated multi-chip module (MCM) transceiver for 4 channel wavelength division multiplexing (WDM) operation, targeting 10 Gbps per channel. We identify five key areas critical to successful integration of MCM transceivers, which we have used in developing our version two MCM transceiver: integration architecture, equivalent circuit model development, PIC to EIC interface modelling, MCM I/O design, and design for assembly.
NASA is working with US industry and academia to develop Photonic Integrated Circuits (PICs) for: (1) Sensors (2) Analog RF applications (3) Computing and free space communications. The PICs provide reduced size, weight, and power that is critical for space-based systems. We describe recent breakthrough 3D monolithic integration of photonic structures, particularly high-speed graphene-silicon devices on CMOS electronics to create CMOS-compatible highbandwidth transceivers for ultra-low power Terabit-scale optical communications. An integrated graphene electro-optic modulator has been demonstrated with a bandwidth of 30 GHz. Graphene microring modulators are especially attractive for dense wavelength division multiplexed (DWDM) systems. For space-based optical communication and ranging we have demonstrated generating a variable number of channels from a single laser using breadboard components, using a single-sideband carrier-suppressed (SSBCS) modulator driven by an externally-supplied RF tone (arbitrary RF frequency), a tunable optical bandpass filter, and an optical amplifier which are placed in a loop. We developed a Return--to-Zero (RZ) Differential Phase Shift Keying (DPSK) laser transmitter PIC using an InP technology platform that includes a tunable laser, a Semiconductor Optical Amplifier (SOA), high-speed Mach-Zehnder Modulator (MZM), and an electroabsorption (EAM) modulator. A Silicon Nitride (SiN) platform integrated photonic circuit suitable for a spectrally pure chip-scale tunable opto-electronic RF oscillator (OEO) that can operate as a flywheel in high precision optical clock modules, as well as radio astronomy, spectroscopy, and local oscillator in radar and communications systems is needed. We have demonstrated a low noise optical frequency combs generation from a small OEO prototypes containing very low loss (~1 dB) waveguide couplers of various shapes and sizes integrated with an ultrahigh-Q MgF2 resonators. An innovative miniaturized lab-on-a-chip device is being developed to directly monitor astronaut health during missions using ~3 drops of body fluid sample like blood, urine, and potentially other body fluids like saliva, sweat or tears. The first-generation system comprises a miniaturized biosensor based on PICs (including Vertical Cavity Surface Emitting Laser – VCSEL, photodetector and optical filters and biochemical assay that generates a fluorescent optical signal change in response to the target analyte.
We demonstrate an optimized silicon photonic link architecture using components from the AIM PDK that achieves an ultra-low sub-pJ/bit power consumption with an aggregate bandwidth of 480 Gb/s. At the transmitter, micro-disk modulators are cascaded along a bus waveguide to select and modulate wavelength-division multiplexed (WDM) channels. At the receiver, micro-ring resonator (MRR) filters are thermally tuned to match the corresponding disks to select from the multiplexed channels. This link architecture yields an ultra-small footprint compared to Mach-Zehnder designs, improving the system scalability and bandwidth density. Additionally, using micro-resonators to select and drop the desired wavelengths from a single bus waveguide allows for straightforward integration with a frequency comb source. The energy performance of the design is optimized through sweeping over three key parameters: (i) optical power per channel, (ii) channel count, and (iii) bitrate. These parameters are the dominant sources for the crosstalk and power penalty in the link design. We identify ideal points in the design space which minimize the energy per bit while staying below the desired bit error rate (BER) of 10-12 and maintaining a realistic aggregate bandwidth. Simulations in the Synopsys OptSim environment using the AIM PDK v2.5a models confirm the functionality of the system with a BER < 10-12, acceptable for both high performance computing (HPC) and data center (DC) applications. Furthermore, optimizing the link energy consumption in the AIM PDK provides a clear path towards low-cost and high-yield fabrication suitable for application in HPC and DC systems.
The cost and complexity of future interconnects create a significant opportunity for emerging photonic tech- nologies such as fibers and switches. These technologies should be evaluated at the system level in order to determine the most efficient way they can be used, as well as provide feedback to photonic developers to better optimize for high-level impact. In this paper, we argue for the need for a systematic methodology to extract system-level models for any emerging photonic component. We then outline our past experience with extracting architectural-level metrics from device demonstrations and conducting architectural-level evaluations. Finally, we discuss qualities for a desirable solution to this problem that requires cross-community collaboration.
This paper presents the integration of multiple silicon photonic (SiP) switches within a high-performance computing environment to enable network reconfigurability in order to achieve optimized bandwidth utilization. We demonstrate a physical testbed implementation that incorporates two fabricated SiP switches capable of switching traffic under real HPC benchmark workloads. The system uses dynamic optical bandwidth steering to match its physical network topology to the traffic characteristics of the application, and achieves up to approximately 40% reduction in application execution time of the high-performance computing benchmark. We present the detailed design of the network architecture and control plane of the system, and discuss the system performance improvements that arises from bandwidth-steering with silicon photonic-based circuit switching.
The first generation of silicon photonic products is now commercially available. While silicon photonics possesses key economic advantages over classical photonic platforms, it has yet to become a commercial success because these advantages can be fully realized only when high-volume testing of silicon photonic devices is made possible. We discuss the costs, challenges, and solutions of photonic chip testing as reported in the recent research literature. We define and propose three underlying paradigms that should be considered when creating photonic test structures: Design for Fast Coupling, Design for Minimal Taps, and Design for Parallel Testing. We underline that a coherent test methodology must be established prior to the design of test structures, and demonstrate how an optimized methodology dramatically reduces the burden when designing for test, by reducing the needed complexity of test structures.
We report a hybrid integrated external cavity laser by butt coupling a quantum dot reflective semiconductor optical amplifier and a silicon-on-insulator chip. The device lasers at 1302 nm in the O-band, a wavelength regime critical to data communication systems. We measured 18 mW on-chip output power and over 50-dB side-mode suppression ratio. We also demonstrated open eye diagrams at 10 and 40 Gb/s.
Performance scalability of computing systems built upon chip multiprocessors are becoming increasingly constrained by limitations in power dissipation, chip packaging, and the data throughput achievable by the interconnection networks. In particular, today’s systems based on electronic interconnects suffer from a growing memory access bottleneck as the speed at which processor-memory data can be communicated out of the chip package is severely bounded. Silicon photonics provide a CMOS-compatible solution for integrating high bandwidth-density off-chip optical I/O which can overcome some of these packaging limitations while adhering to pJ/bit-scale power efficiency requirements. Microrings in particular pose an attractive option for realizing optical communication functionalities due to their low footprint, low power dissipation, and inherent WDM-suitability due to their wavelength-localized operation. We analyze a terabit-per-second scale microring-based optical WDM link composed of current best-of-class devices. Our analysis provides quantitative measures for the maximal achievable bandwidth per link that could be reasonably realized within several years. We account for the full optical power budget to determine the achievable bandwidth as well as to enable a power consumption analysis including transmit and receive circuitry, photonic-device power dissipation, and laser power. The results highlight key device attributes that require significant advancement and point out the need for improvements in laser wall-plug efficiencies to provide sub-pJ/bit scale optical links.
We introduce a multi-layer silicon photonic microring resonator filter, fabricated using deposited materials, and transmit
up to 12.5-Gb/s error-free data, establishing a novel class of high-performance silicon photonics for advanced photonic
NoCs. Furthermore, by leveraging deposited materials, we propose a novel fully-integrated scalable photonic switch
architecture for data center networks, sustaining nonblocking 256×256 port size with nanosecond-scale switching times,
interconnecting 2,560 server racks with 51.2-Tb/s bisection bandwidth.
We show wavelength conversion and wavelength multicasting using four-wave mixing in silicon waveguides, achieving
record performance in both bandwidth and bit rates in this CMOS-compatible platform. Non-return-to-zero data at 10-
and 40-Gb/s bit rates is wavelength converted across nearly 50 nm, with error-free transmission. Bit-rate transparency of
the all-optical process is demonstrated by converting up to 160-Gb/s return-to-zero data. In addition, an eight-way
wavelength multicast of 40-Gb/s data is shown using the same silicon waveguide platform, with error-free transmission.
The communication performance is evaluated using measured eye diagrams, bit-error rates, and power penalty
In the continual drive toward improved microprocessor performance, power efficiency has emerged as a prime design consideration. At the chip scale, the trend toward multi-core architectures and chip multiprocessors (CMPs) for driving performance-per-watt via increases in the number of parallel computational cores is dominating new commercial releases. The role of the interconnect and associated global communication infrastructure is becoming central to the chip and ultimately computing system performance. On-chip photonic communication has been recently explored to address the communication requirements in future high-performance CMPs. We have developed a photonic network simulation environment that uniquely incorporates physical layer silicon photonic device models. We report on the design optimization of the network micro-architecture layout and photonic switching fabric organization. The event-driven network simulator establishes physical layer metrics for the silicon photonic devices and provides a measure of the network performance-per-Watt requirements derived from device characteristics.
The emerging class of multicore architectures and chip multiprocessors (CMPs) has
fundamentally shifted the impact of communications on computing systems performance. Global
communications at all scales is playing a central and dominant role in the ultimate realization of
CMP system performance as it falls increasingly on the efficiency of the information exchange
among the vastly growing number of compute and memory resources. In this new
communication-bound paradigm, the realization of a system-wide scalable communications
infrastructure that can meet the enormous bandwidths, capacities, and stringent latency
requirements in an energy efficient manner is a key goal for scaling future computation
performance. We explore how recent extraordinary advances in nanoscale silicon photonic
technologies can be exploited for developing optical interconnection networks that address the
critical bandwidth and power challenges presented across several levels of the CMP computing
system communications infrastructure. Unlike prior generations of photonic technologies, the
remarkable capabilities of nanoscale "CMOS photonics" offer the possibility of creating highly integrated
platforms for generating and receiving optical signals with fundamentally superior
power efficiencies. Optical interconnection network architectures employing these silicon
nanophotonic building blocks are uniquely co-developed and explored in the context of
bandwidth-driven computing models. The design of an on-chip optical interconnection network
that employs nanoscale CMOS photonic devices and enables seamless off-chip communications
to other CMP computing nodes and to external memory is described.
Higher data throughput in optical packet switched interconnection networks can be achieved by minimizing the guard times through faster transition of the switching element. A hybrid integration of a semiconductor optical amplifier with its current driver is presented, which exhibits over 40% faster transition time compared to current commercial devices.
Photonic packet switching for all-optical networks is a rapidly developing technology since it circumvents many of the traditional bottlenecks created by the use of electronics. All-optical networking has application to both long-haul communications systems and high-performance computing systems. In each case, all-optical technologies are responsible for the routing, switching and logic decisions of the network. Characterizing the performance of a network includes calculating the latency and scalability of a given architecture assuming ideal behavior of its physical components. However, the physical layer ultimately determines the feasibility of data transmission. Thus accurately calculating the accumulated bit-error-rate (BER) is fundamental to evaluating the optical network as a whole, regardless of the network architecture. A new simulation technique, which is based upon experimental findings, is introduced which characterizes the physical layer performance of a given network architecture known as the Data Vortex. Experiments show that almost all the physical layer penalty is generated by the nodes which are used for switching and routing. Specifically, at each node data packets are amplified by a semiconductor optical amplifier so that coupling and routing losses are compensated. In this process, the data packets receive a noise penalty which results primarily from amplified spontaneous emission and in small part from spectral broadening. By using a phenomenological approach to modeling the noise penalties, the performance of the network nodes can be characterized. The modeling allows for a comprehensive understanding of the network and is a highly efficient computational tool for evaluating performance when compared to conventional time-domain techniques.
Backbone optical systems with ever-increasing transport capacity and routing complexity are driving the need for large port count core switches that can intelligently scale to manage the amounting bandwidth mass. Optical switching fabrics and in particular those based on MEMS technology potentially offer a scalable solution for the cross-connect network element. However the road from this exciting research endeavor to creating a reliable and manufacturable product is filled with challenges. The design, integration, and assembly of optical switch fabrics with over 1000 working ports stress all aspects of product development from component fabrication to mechanical tolerances and thermal manageability. In this paper we describe the myriad of contending optical, mechanical, and electronic design tradeoffs that contribute to the development of a 3D-MEMS based optical cross-connect.
A new optical packet switching network and its enabling technologies are investigated for implementation in a Petaflops scale supercomputer system. We capitalize on the immense bandwidth of the optical fiber interconnects by deploying WDM/TDM packet payloads. To accommodate current optical switching technologies, the routing operations in the network are drastically simplified and the need for buffering is completely eliminated. This paper presents the experimental demonstration of the routing within the unique packet switched architecture. Multiple node hops are demonstrated in a node test-bed environment with a re- circulating loop configuration.
Passively modelocked fiber lasers operating in the soliton regime can generate pulses at multi-gigahertz harmonic repetition rates. The lasers are modelocked with an ultrafast saturable absorber and the low loss cavities support the formation of multiple equally spaced soliton pulses. These sources are potentially attractive for applications in high speed fiber optic communications systems. The design and construction of these laser sources as well as their application to spectrally sliced wavelength division multiplexed transmission is described.