With the adoption of extreme ultraviolet (EUV) lithography for high volume production in the advanced wafer manufacturing fab, defects resulting from stochastic effects could be one of major yield killers and draw increasing interest from the industry. In this paper, we will present a flow, including stochastic edge placement error (SEPE) model calibration, pattern recognition and hot spot ranking from defect probability, to detect potential hot spot in the chip design. The prediction result shows a good match with the wafer inspection. HMI eP5 massive metrology and contour analysis were used to extract wafer statistical edge placement distribution data.
The mask is a known contributor to intra-field and local patterning fingerprints at the wafer level. Traditionally, a 3σ distribution of critical dimensions (CDs) on mask was sufficient to characterize the contribution to the CD distribution at wafer level. However, as edge placement error (EPE) and EUV wafer patterning stochastics become critical with decreasing feature sizes, wafer CD distributions are being characterized for statistics beyond 3σ. Additionally, Local Placement Error (LPE) is a critical metric that is expected to contribute to EPE. Consequently, it is imperative to understand, characterize and control the EUV mask contributors to the EPE budget. This work is an attempt to extensively characterize the CD and LPE distribution on an EUV mask and identify its impact at wafer level.