This paper reports the readiness of key EUV resist process technologies using Metal Oxide Resist (MOR) aiming for the DRAM application. For MOR, metal contamination reduction and CD uniformity (CDU) are the key performance requirements expected concerning post exposure bake (PEB). Based on years of experience with spin-on type Inpria MOR, we have designed a new PEB oven to achieve contamination mitigation, while keeping our high standard of CDU. The new bake oven was introduced in our coater and developer and evaluated using line/space patterns. As described in the results, exceptional CD uniformity was realized while exceeding the metal contamination specification. The new plate design also enabled a 30% reduction in dose-to-size without degradation of CDU when applying higher PEB temperature. Another challenge for the DRAM application in particular is pattern collapse as applied to pillar patterns. By optimization of several parameters, the pattern collapse margin extended the minimum CD by 13.8%. The result was achieved with a combination of SiC in place of SOG for under layer, thinner resist film thickness and a modified resist material, MOR-B. Finally, to achieve target yield performance, defectivity reduction is also an important task towards MOR application. An integrated approach is needed to realize scum free patterning because if metal residuals remain in the open space, they can cause yield-killing defects. By analyzing possible root causes of defect sources, we attempt to eliminate etch-masking scum layer present after conventional developer processing. By applying a post develop rinse including novel hardware for defect reduction, bridge defects were reduced up to 19% with new the technology.
Extreme ultraviolet (EUV) materials are deemed as critical to enable and extend the EUV lithography technology. Currently both chemically amplified resist (CAR) and metal-oxide resist (MOR) platforms are candidates to print tight features on wafer, however patterning requirements, process tonality (positive or negative), illumination settings and reticle tonality (dark or bright) play a fundamental role on the material performance and in consequence on the material choice.
In this work we focus on the patterning of staggered pillars using a single EUV exposure, and this by looking at the lithographic and etching performance of CAR and MOR platforms, using metrics as process window, local critical dimension uniformity (LCDU), pillar edge roughness (PER), pillar placement error (PPE) and (stochastic) nano-failures.
As a bright field reticle shows a lower aerial image contrast to print pillars compared to the aerial image of contact holes using a dark field reticle, we also investigate alternative patterning solutions such as the tone reversal process (TRP) to pattern pillars from contact holes.
In order to continue scaling down the feature sizes of the devices, EUV lithography is regarded as the most
powerful candidate for patterning. So It has being studied to overcome the several issues such as source
power for high throughput to apply volume production, mask defectivity from mask blank, RLS (Resolution,
LWR & Sensitivity) trade off, which is the intrinsic property of EUV resist, and so on.
For 2x nm node DRAM, dense contact hole, which has 3x nm half pitch (hp), has been issued to be made so
far. There are two well-known methods for pattering; hole double patterning with ArF immersion lithography
and single patterning with EUV lithography. EUV is more simple solution than hole double patterning for
3xnm hp dense contact hole, if it has large process window and comparable CD uniformity. Fortunately,
EUV process already has larger process window than that of ArF immersion because its k1 value is a little bit
high. But CD (critical dimension) uniformity and pattern profile were very poor in our initial result.
Therefore it needs a lot of efforts to improve and compete against double patterning.
The double patterning performance for 3xnm hp contact hole has been shown last year. In this paper, we
will investigate on improving CD uniformity and pattern profile for 3x nm hp contact hole with several
methods. Finally, the performance of EUV, which is achieved by our experiments, is being compared with
that of double patterning in terms of CD uniformity and pattern profile.
In order to continue scaling down the feature sizes of the devices until extreme ultraviolet lithography (EUVL) reaches
to production capability, the alternative methods such as double patterning technology (DPT) and spacer patterning
technology (SPT) are applied for half pitch (hp) 2x~3x nm line / space imaging. In the storage node of DRAM, both
stable hole patterning and high dielectric constant (ε) material development are key factors to secure the capacitance. In
terms of hole patterning, we anticipate that hp 4x nm hole will be possible with combination of vertical and horizontal
lines. However, the patterning process for hp 3x nm hole has to find a solution in trade-off relationship between process
stability, complexity and cost of ownership (CoO) until EUVL is accomplished. In this paper, we will demonstrate 3x
nm hole patterning process using double patterning technology combined with negative tone development (NTD).
Contrary to general method (positive tone development with dark field mask) for hole patterning, intention to use NTD
with bright field mask will first be discussed. Evaluation and analysis of the simulated and experimental results will be
discussed for block CD uniformity improvement. In addition to patterning, overlay performance will be tested through
NXT 1950i to confirm DPT process feasibility. Finally, process integrations including etch process will be
demonstrated.
Contact hole patterning is more difficult than line/space patterning as mask error factor is higher in contact hole
patterning which has 2-dimensional patterns. As the industry moves towards 40nm node and beyond, the challenges
associated with contact hole having a manufacturable process window have become increasingly difficult. Current
1.35NA ArF lithography is capable of printing 50nm contact hole with a stable process window at best. Conventional
contact hole patterning processes such as resist reflow and RELACS are no longer able to be used for half-pitch 40nm
contact hole pattern because we have to shrink not only hole diameter but also pattern pitch. In this paper, we will
demonstrate and compare the patterning performance of the mesh patterning processes including litho-etch-litho-etch, cap freezing and self freezing process.
When patterning critical layers at hyper NA, a multilayer antireflectant system is required in order to control
complex reflectivity resulting from various incident angles. Multilayer antireflectants typically consist of an
organic antireflectant and inorganic substrates. However, there are still some applications which need a single
organic antireflectant over high reflective substrates. A 2P2E application in double patterning is one of them.
Even though the pitch for double patterning is relatively loose, the reflectivity control is still challenging in terms
of profiles and overall process window. The optical constants and thickness of antireflectants should be well
optimized depending on applications. We have investigated several organic antireflectants for a single
antireflectant over high reflective substrates. The organic films differ in terms of n, k, thickness to cover both the
1st minimum and the 2nd minimum applications. The overall patterning performance including profiles and
process window has been evaluated. ASML 1900i was used to perform lithography. Simulation was performed
using ProlithTM software.
In recent years, DRAM and Flash technology node has shrunk below to 45nm half pitch (HP) patterning with significant progresses of hyper numerical aperture (NA) immersion lithography system and process development. Several technologies such as extreme ultra violet (EUV) lithography, double patterning technology (DPT) and spacer patterning technology (SPT) have been developed for sub 40nm HP device. High index immersion lithography (HIL) is also one of the candidates for next generation lithography technology that has benefits of product cost, process simplification and usage for existing infrastructure though this technology must overcome critical issues--high index immersion fluid and lens optic development.
In this paper, we will present simulation results on sub 40nm imaging characterization for HIL.
First, we have studied the image performance for sub 40nm patterning with HIL. The image contrast, optical proximity effect and mask error enhanced factor (MEEF) are investigated through simulation. As pattern size decrease and lens NA gets bigger and bigger, the features on mask get smaller even below the wavelength of light and polarization related effects become one of the most critical issues. From comparison with results for 45nm HP patterning, we are able to suggest the reasonable process condition for HIL process.
Then, we have investigated the optimum BARC condition to make preparations for 32nm HP pattering.
KEYWORDS: Reflectivity, Photoresist materials, Etching, Immersion lithography, System on a chip, Lithography, Polarization, Carbon, Process control, Polymers
The extension of current 193nm immersion lithography technology is depending on increasing the numerical aperture
(NA). High-resolution imaging requires the decrease of photoresist thickness to compensate for smaller depth of focus
(DOF) and prevent pattern collapse. Poor etch selectivity between photoresist and BARC reads to the use of thinner
BARC with faster etch-rate.
Also, controlling reflectance over a wider range of incident angles for hyper-NA above 1.0 gives more challenge for
thin BARC. To reduce substrate reflectivity, various material strategies (dual-layer BARC such as organic/inorganic
BARC or organic/organic BARC, Si-based ARC/spin-on carbon (SOC), and so on) have been introduced through many
papers. Organic dual-layer BARC is capable of suppressing reflectivity through wide range of incident angles. But,
the inevitable increase of its thickness is not a desirable direction due to the decreasing trend of photoresist thickness.
When amorphous carbon (a-C) is used as a hardmask for sub-stack, the combination of organic/inorganic BARC (i.e.
SiON) is currently well known process. Si-ARC/SOC may be the promising candidates of hardmask because Si
component of Si-ARC affords a high etch selectivity to photoresist and its combination with SOC decreases reflectance.
The optical constants of above organic materials can be tuned to control the substrate reflectivity for hyper-NA.
Most semiconductor companies are using Bottom Anti-Reflective Coating (BARC) on their lithography process to
reduce bottom reflectivity, which is cause of standing wave, pattern collapse, and bad pattern profile, and to improve
lithographic performance. BARC has been diversified to adapt to the wavelength of exposure light and refractive indices
of photoresists and substrates. Recently, many semiconductor companies introduce new process, such as immersion
process and double patterning process, to get high resolution for next generation semiconductor and they are trying to
apply these processes to their mass production. Among those process solutions, a strong candidate for high resolution is
introduction of hyper NA(Numerical Aperture) exposure tool, using immersion process. There is one thing to solve for
BARC material when immersion process is applied. It is reflectivity. As NA of exposure tool increases, reflectivity from
a substrate also increases, simultaneously. We simulated the difference of reflectivity with increasing NA and we found a
proper way how to control reflectivity on immersion process with refractive indices of BARC. We will report simulation
data for immersion process and introduce our new developed BARC for hyper NA process in this paper.
Silicon-containing material has recently attracted attention as new hard mask material. We have studied the applicability
of MFHM (Multi-Functional Hard Mask)/SOC (Spin on Carbon) materials as an alternative to the BARC/SiON/
amorphous carbon (a-C) process. This process is very useful in terms of cost reduction and process simplicity compared
to a-C process. Evaluation results have showed good lithographic and etch performances. However, this MFHM process
has showed specific defects related to material. This paper will focus on defect type and suggest its solution.
ArF lithography has been driven into sub-100 nm dimensions using high numerical apertures, phase-shift mask,
modified illumination, and optical proximity correction. As feature size continues to shrink, photoresist thickness as an
imaging layer has been decreased for the improvement of lithographic process window and pattern collapse margin.
Moreover, ArF photoresist has the inherent demerit of poor etch resistance in comparison with KrF photoresist and we
have to use inorganic hard mask materials such as silicon-nitride, -oxide, poly-silicon, and silicon oxynitride as a
pattern transfer layer. The cost-of-ownership (COO) of CVD process related to the application of inorganic hard mask
is much more expensive than that of spin-on process. Therefore, several processes including bi-layer resist process
(BLR), and tri-layer resist process (TLR)1 have been investigated. This paper will focus on TLR process consisted of
multi-function hard mask (MFHM) material and spin on carbon (SOC) material.
ArF lithography has shrunk photo resist patterns down to 60nm from 80nm with the help of various RETs (resolution enhancement technologies). Photo resist thickness also has been thinner than ever to increase image contrast and DoF margin and to avoid pattern collapse due to high aspect ratio. Etching process became more difficult and marginal by using thin resist patterning so that new BARC materials having high etching selectivity are required. Since amorphous carbon (a-C) and SiON have good etch selectivity between them, they can be used as hard mask materials for thin resist process. Lithographic alignment system usually uses the light of 400 to 700nm. In general a-C has certain level of light absorption in this wavelength range and the absorption coefficient increases with deposition temperature of a-C. Because a-C film is not suitably transparent to the alignment light, overlay control might get worsen as the thickness of a-Carbon film increased. In this paper, we will present the effect of the thickness of a-Carbon film on alignment signal strength, alignment accuracy and overlay control of various layers. Simulation of alignment signal is conducted and compared with experiment results. It is also studied whether the overlay control can be improved by changing the spectrum of alignment light or structural design of alignment marks. Improvements on alignment accuracy and overlay control are examined by lowering the extinction coefficient, k of a-Carbon film.
In conclusion, because photo resist only is not sufficient for a mask during etch step as the thickness decreased further, adoption of new hard mask is inevitable. It is the alignment trouble for a-Carbon that should be cleared before being named as a main stream of new hard mask.
512Mbit DRAM with 70 nm design rule was tailored using 0.31k1 ArF lithography technologies. Of the critical mask layers, four pattern layouts were demonstrated: brick wall, line/space, contact and line/contact patterns. For the sake of cost reduction, the conventional technologies were used. Results has shown that SLR (Single-Layer Resist) process, half-tone PSM and the conventional illuminations had a potential of manufacturing 70 nm DRAM. However, it was found that brick wall patterns had asymmetrical shape and total CD uniformity was out of target raging 9.2 nm through 16.3 nm depending mask layouts. We prospect that higher contrast resist and more elaborate resist process will address these problems sooner or later. In case the immersion lithography is not ready around the right time, the feasibility of 0.29k1 ArF lithography was studied through simulation and test, which represented that 0.29k1 technologies were likely to be applied for the development of 60 nm DRAM with the aid of RETs (Resolution Enhancement Technologies) including customized illumination and new hard mask process.
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