In recent years it has become apparent that power supply voltage drops during circuit operation can result in abnormal operations in ULSI semiconductor chips. To resolve this problem, we have inserted a decoupling capacitor into our products. This paper presents insertion methods for internal decoupling capacitors to reduce the voltage-drop problem in chemical mechanical polish (CMP) and ultra large-scale integration (ULSI).
A decoupling capacitor has a high pattern density leading to high density locally in the domain in which it is placed. Consequently, arranging conventional decoupling capacitors is problematic for CMP and lithography due to insufficient depth of focus (DOF).
In this study, we first review and develop estimates for the decoupling capacitor and area fill insertions and propose an imitation dummy pattern comprising decoupling capacitors. We then perform an analysis to determine if there is an effective decrease in voltage drop without diminished yield. Finally, we evaluate the proposed techniques using layout test cases from industry.
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