Europe has currently no full supply chain of CMOS image sensors (CIS) for space use, certainly not in terms of image sensor manufacturing. Although a few commercial foundries in Europe manufacture CMOS image sensors for consumer and automotive applications, they are typically not interested in adapting their process flow to meet high-end performance specifications, mainly because the expected manufacturing volume for space imagers is extremely low.
Backside illuminated (BSI) hybrid CMOS image sensors possessing excellent spectral response
(> 80% between 400nm-800nm) have been previously reported by us. Particularly challenging with BSI imagers is to
combine such sensitivity, with low electrical inter-pixel crosstalk (or charge-dispersion). Employing thick bulk silicon
(in BSI) to maximize red response results in large crosstalk especially for blue light. In the second generation of these
imagers, we undertook the exercise of solving the crosstalk problem by a two-pronged approach: a) an optimized
epitaxial substrate that was engineered to maximize the internal electric field b) high aspect ratio trenches (30 μm deep)
with carefully tailored sidewall passivation. The results show that the proposed optimizations are effective in curtailing
crosstalk without having a major impact on other sensor parameters.
Two types of backside illuminated CMOS Active Pixel Detectors--optimized for space-borne imaging--have been
successfully developed: monolithic and hybrid. The monolithic device is made out of CMOS imager wafers postprocessed
to enable backside illumination. The hybrid device consists of a backside thinned and illuminated diode array,
hybridized on top of an unthinned CMOS read-out. Using IMEC's innovative techniques and capabilities, 2-D arrays
with a pitch of 22.5 μm have been realized. Both the hybrid and well as the monolithic APS exhibit high pixel yield, high
quantum efficiency (QE), and low dark current. Cross-talk can be reduced to zero in the hybrid sensors utilizing special
structures: deep-isolating trenches. These trenches physically separate the pixels and curtail cross-talk. The hybrid
imagers are suitable candidates for advanced "smart" sensors envisioned to be realized as multi-layer 3D integrated
systems. The design of both these types of detectors, the key technology steps, the results of the radiometric
characterization as well as the intended future developments will be discussed in this paper.
We report first results of laboratory tests of Si:As
blocked-impurity-band (BIB) mid-infrared (4 to 28 μm) detectors developed
by IMEC. These prototypes feature 88 pixels hybridized on an integrated cryogenic readout electronics (CRE). They
were developed as part of a technology demonstration program for the future Darwin mission. In order to be able to separate
detector and readout effects, a custom build TIA circuitry was used to characterize additional single pixel detectors.
We used a newly designed test setup at the MPIA to determine the relative spectral response, the quantum efficiency, and
the dark current. All these properties were measured as a function of operating temperature and detector bias. In addition
the effects of ionizing radiation on the detector were studied. For determining the relative spectral response we used a dualgrating
monochromator and a bolometer with known response that was operated in parallel to the Si:As detectors. The
quantum efficiency was measured by using a custom-build high-precision vacuum black body together with cold (T ~ 4K)
filters of known (measured) transmission.
This paper reports on the fabrication and characterization of a linear array of Blocked Impurity Band (BIB) far infrared detectors and of the related Cryogenic Readout Electronics (CRE). It is part of the ESA DARWIN project which aims at the study of exoplanets by means of null interferometry and requires high performance infrared detector arrays in the 6 18μm range. Si:As BIB detectors have been fabricated on an infrared transparent Silicon substrate enabling backside illumination. The buried contact, the active and the blocking layers are deposited by epitaxy; the doping profile is controlled by adjusting the growth parameters. Access to the buried contact is provided by anisotropic silicon etch of V-grooves in the epi layers. Spray coating of photoresist is used for the lithography of the wafers with high topography. The CRE is composed of an input stage based on an integrating amplifier in AC coupled feedback with selectable integrator capacitors, of a sample and hold stage which provides isolation between input and sampling capacitance, and of an output buffer with multiplexing switch. The readout is optimized for low noise with minimum operating temperature of 4K. Linear arrays made of 42 and 88 detectors and having 30μm pixel pitch with various active areas are fabricated. Detector arrays are coupled to the CRE by Indium bumps using flip-chip technology. Measurements on the readout show reduced noise, good linearity and dynamic range. First detector characterization results are presented.
The ultra-high density hybrid flip chip integration of an array of detectors and its dedicated readout electronics can be achieved with a variety of solder bump techniques such as pure Indium of Tin alloys, (In, Ni/PbSn), but also conducting polymers, etc. Particularly for cooled applications or ultra-high density applications, Indium solder bump technology (electroplated or evaporated) is the method of choice. The state-of-the-art of solder bump technologies that are to a high degree independent of the underlying detector material will be presented and examples of interconnect densities between 5e4/cm2 and 1e6/cm2 will be demonstrated.
For several classes of detectors, flip-chip integration is not allowed since the detectors have to be illuminated from the top. This applies to image sensors for EUV applications such as GaN/AlGaN based detectors and to MEMS-based detectors. In such cases, the only viable interconnection method has to be through the (thinned) detector wafer followed by a based-based integration. The approaches for dense and ultra-dense through-the-wafer interconnect "vias" will be presented.