Roughness of lithographic patterns is typically expressed as the absolute 3σ variation of resist lines by means of edge variation. However, full characterization of the roughness requires both its amplitude and frequency distribution. This necessity arises from the requirement to reduce different roughness frequencies for different lithographic levels. The International Technology Roadmap of Semiconductors (ITRS) has established a dedicated specification for low frequency roughness. To obtain full knowledge of the roughness behavior in the frequency domain, a power spectral density analysis technique is used. It is found that power spectral density has a unique profile for each process. Moreover, the major contribution to the roughness came from the low frequencies range. Besides this, an on-line metrological study on scanning electron microscopy resist roughness repeatability is executed to optimize the capturing image parameters and estimate eventual short- (daily) and long-term (yearly) contributions. In the end, 0.2-nm 3σ line width roughness stability value is found. To verify the validity of analysis and metrology, 32-nm extreme ultraviolet lithography exposures at different flare levels, 45-nm ArF immersion lithography through dose, and a rinse postlithography smoothing process are characterized with the aim to highlight the importance of low frequency roughness detection.
The model-based library (MBL) matching technique was applied to measurements of photoresist patterns exposed with a
leading-edge ArF immersion lithography tool. This technique estimates the dimensions and shape of a target pattern by
comparing a measured SEM image profile to a library of simulated line scans. In this study, a double trapezoid model
was introduced into MBL library, which was suitable for precise approximation of a photoresist profile. To evaluate
variously-shaped patterns, focus-exposure matrix wafers were exposed under three-illuminations. The geometric
parameters such as bottom critical dimension (CD), top and bottom sidewall angles were estimated by MBL matching.
Lithography simulation results were employed as a reference data in this evaluation. As a result, the trends of the
estimated sidewall angles are consistent with the litho-simulation results. MBL bottom CD and threshold method 50%
CD are also in a very good agreement. MBL detected wide-SWA variation in a focus series which were determined as in
a process window by CD values. The trend of SWA variation, which is potentiality to undergo CD shift at later-etch step,
agreed with litho-simulation results. These results suggest that MBL approach can achieve the efficient measurements for process development and control in advanced lithography.
With the improved resolution of immersion lithography by Hyper-NA (Numerical Aperture) and Low-k1 scaling factor,
lithographers face the problem of decreasing Depth of Focus and in turn reduced process latitude. It is important for
high precision process monitoring the decrease in process latitude which comes with Hyper-NA and Low-k1, in order to
be able to successfully introduce RET (Resolution Enhancement Techniques) lithography into high volume production.
MPPC (Multiple Parameters Profile Characterization) is a function which provides the ability to extract pattern shape
information from a measured e-beam signal. MPPC function becomes key technique of pattern profile verification by
top down SEM images for the Hyper-NA lithography, for that reason it can be detected to relate to pattern profile
change.
In this work, we explored a practical application of MPPC function by making clear the relationship between MPPC
indices and Litho parameters concerning specific lithography application. We performed the two kinds of experiment
for verifying effectiveness of the MPPC function. First experiment explored printing image contrast by using the WB
with exposure pattern shape change related from image printing condition. Second experiment explored pattern shape
change due to resist contrast with changing the process conditions by using WB behavior. In consequence, we
demonstrated a practical application of MPPC function by quantification using WB and assessed the process monitoring
capability.
Our challenge of this research is the practical application of the MPPC function on production wafers concerning
specific lithography application. We believe that this application can be effectual in process monitoring and control for
Hyper-NA lithography.
In this research, we improved litho process monitor performance with CD-SEM for hyper-NA lithography. First, by
comparing litho and etch process windows, it was confirmed that litho process monitor performance is insufficient just
by CD measurement because of litho-etch CD bias variation. Then we investigated the impact of the changing resist
profile on litho-etch CD bias variation by cross-sectional observation. As a result, it was determined that resist loss and
footing variation cause litho-etch CD bias variation. Then, we proposed a measurement method to detect the resist loss
variation from top-down SEM image. Proposed resist loss measurement method had good linearity to detect resist loss
variation. At the end, threshold of resist loss index for litho process monitor was determined as to detect litho-etch CD
bias variation. Then we confirmed that with the proposed resist loss measurement method, the litho process monitor
performance was improved by detection of litho-etch CD bias variation in the same throughput as CD measurement.
KEYWORDS: Scanning electron microscopy, Critical dimension metrology, Signal detection, Lithography, Signal attenuation, Semiconducting wafers, Process control, 3D metrology, Finite element methods, Metrology
In our previous paper*[1], next generation lithography offering improved resolution by use of Hyper-NA and Low-k1,
changes in exposure tool focus were seen to influence pattern shape and it was verified that pattern profile variation
occurs even when measured CD values are similar. This shows the necessity for process control to include pattern
shape information, conventional methods using the CD value alone will be insufficient as process latitudes continue to
shrink. In such a situation, to be able to precisely measure the physical dimensions of design features becomes more
and more important.
In this study, we have investigated improved precision of Process Window (PW) determination by using the MPPC
function that allows the pattern profile shape to be quantified. We have also evaluated pattern shape variation by
means of Litho-simulation. As a result, it was confirmed that resist loss is the main change in shape that occurs.
Therefore, we have focused our attention on resist loss and optimized the MPPC parameters by SEM simulation*[2].
As a consequence, it was possible to precisely detect the resist loss. Using this technique, it was possible to show the
possibility for highly precise 3D measurement determination, for use in exposure tool monitoring, by using the MPPC
measurement technique.
KEYWORDS: Etching, Semiconducting wafers, Transistors, Field effect transistors, Scanning electron microscopy, Scatterometry, 3D metrology, Edge roughness, Metrology, Process control
Multiple Gate Field Effect Transistors (MuGFETs) have been proposed to enable downsizing, when scaling
the transistors to the 32nm technology node. The dimension of the gate on the surface of fin determines the
effective channel length of the device. So, the characterization of the gate profiles at fin sidewalls becomes
extremely critical. It is especially important to quantify the rounded intersection (etch residual) at the
intersection of the fin and gate.
In this report, we show top down images of a MuGFET taken with critical-dimension scanning electron
microscopy (CD-SEM) and the results that were measured and characterized by measuring various portions of
the pattern which will impact the MuGFET performance i.e. gate length, fin width. We will introduce a
quantified relation between fin length and "its effect on the etch residue at the intersection of fin and gate".
Next we discuss our approaches to analyze the variation of the shape of the gate at the fin sidewall.
With the recent introduction of immersion lithography, optical systems with numerical aperture (NA) reaching 1.0 or
larger can be realized. Various Resolution Enhancement Techniques (RET) such as various phase shift mask approaches
have been used to push even further the resolution limit by reducing k1 scaling factor, including Double Patterning
Technology. However, with the improved resolution by Hyper-NA and Low-k1, lithographers face the problem of
decreasing Depth of Focus and in turn reduced process latitude. Throughout the industry, Process Window has been
widely used as an analytical tool to evaluate process latitude for a given design feature size; therefore, the ability to
accurately and efficiently derive a Process Window within which a process can run on target and in control is
fundamental to Low-k1 lithography. Accuracy of Process Window derivation is based on the ability to accurately
measure and model the physical dimension of the design feature and how it changes in response to changes in process
parameters. In the case of lithography, the Process Window of a desired critical dimension target is bounded by
changes in exposure energy and defocus. To be able to accurately measure the physical dimension of the design
feature remains a big challenge for metrologists especially in the presence of other process noise. In this work, it is
shown that the precision of PW measurement can be enhanced by using CD-ACD (Average CD) function to measure a
FEM (Focus-Exposure matrix) wafer. ACD is a function, which simultaneously measures several points, thus
providing higher precision measurement in comparison to the conventional single point measurement. As seen in this
work, by using ACD measurements to derive the Process Window, there is a significantly improvement in the stability
of the derived Process Window. Also reported is the MPPC (Multiple Parameters Profile Characterization) *1), a
function which provides the ability to extract pattern shape information from a measured e-beam signal. This function
together with the ACD function enables PW measurement with high precision, which also takes into account the actual
pattern shape. PW derived from conventionally measured data was compared with PW derived from ACD and MPPC
measurement and we were able to demonstrate an improvement of more than 30% in precision of PW determination.
This paper describes a new method of self-calibration for use in step-and-repeat projection aligners. In order to obtain a higher alignment accuracy, it is important to decrease all kinds of stepper fluctuations. In conventional aligners an automatic calibration system, that uses a special reticle for calibration, was proposed. However, the new method uses the usual reticles which have four special small marks on the surrounding region of the device pattern area. Furthermore, only a small detector embedded in the portion of the wafer stage is required for this self-calibration. Therefore, this new system will be implemented easily in any kind of stepper and it can calibrate anytime before exposure. Moreover, the stepper's offsets, such as alignment, focusing, chip rotation and magnification, are all calibrated at the same time. Based on the results, the improvement of the stepper stability is verified in production use level. Moreover, the use of this system for stepper control can also improve stepper through-put.
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