The ever-increasing energy consumption of Data Centers (DC), along with the significant waste of resources that is observed in traditional DCs, have forced DC operators to invest in solutions that will considerably improve energy efficiency. In this context, Rack- and board-scale resource disaggregation is under heavy research, as a groundbreaking innovation that could amortize the energy and cost impact caused by the vast diversity in resource demand of emerging DC workloads. However disaggregation, by breaking apart the critical CPU-to-memory path, introduces a challenging set of requirements in the underlying network infrastructure, that has to support low-latency and high-throughput communication for a high number of nodes.
In this paper we present our recent work on optical interconnects towards enabling resource disaggregation both on Rack-level as well as on board-level. To this end, we have demonstrated the Hipoλaos architecture that can efficiently integrate Spanke-based switching with AWGR-based wavelength routing and optical feedforward buffering into highport switch layouts. The proof-of-concept Hipoλaos prototype, based on the 1024-port layout, provide latency performance of 456ns, while system level evaluations reveal sub-μs latency performance for a variety of synthetic traffic profiles. Moving towards high-capacity board-level interconnects, we present the latest achievements realized within the context of H2020-STREAMS project, where single-mode optical PCBs hosting Si-based routing modules and mid-board optics are exploited towards a massive any-to-any, buffer-less, collision-less and extremely low latency routing platform with 25.6Tb/s throughput. Finally, we combine the Hipolaos and STREAMS architectures in a dual-layer switching scheme and evaluate its performance via system-level simulations.
The rapid increase of bandwidth requirements across the entire hierarchy of Data Center (DC) networks, ranging from chip-to-chip, board-to-board up to rack-to-rack communications, puts strenuous requirements in the underlying network infrastructure that has to offer high-bandwidth and low-latency interconnection under a low-energy and low-cost envelope. Arrayed Waveguide Grating Router (AWGR)-based optical interconnections have emerged as a powerful architectural framework that can overcome the currently deployed electrical interconnect bottlenecks leveraging the wavelength division multiplexing (WDM) and the cyclic routing properties of AWGRs to offer one-hop, all-to-all communication when employed as N×N routers. However, the majority of previous silicon (Si)-based integrated AWGR demonstrations has either targeted C-band operation, despite the dominance of the O-band spectral region in the DC interconnection domain, or offered coarse-WDM (CWDM) functionality and, as such, were limited in terms of AWGR port count. In this article, we present for the first time to our knowledge, a Dense-WDM (DWDM) 16×16 Si-photonic cyclic-frequency AWGR device targeting O-band routing applications. The fabricated AWGR device features a channel spacing of 1.063 nm (189 GHz), a free spectral range of 17.8 nm (3.15 THz) and a 3-dB bandwidth of 0.655 nm (116 GHz). Its proper cyclic frequency operation was experimentally verified for all 16 channels with channel peak insertion loss values in the range of 3.9 dB to 8.37 dB, yielding a channel loss non-uniformity of 4.47 dB. Its compact footprint of 0.27×0.71 mm2 and low crosstalk of 21.65 dB highlight its potential for employment in future AWGR-based interconnection schemes.