An advanced photomask is rarely made meeting all specifications in one attempt. In the photomask industry, yield is the critical component to all key performance measures including cost and delivery time. Defect-free advanced masks are extremely difficult to manufacture but leading-edge masks simultaneously meeting atomic level pattern placement, angstrom level CD uniformity, and defectivity to virus size sensitivity are a rarity. While the patterning and inspection segments have been the long-time nemeses of cost, the ideal mask fabrication process will perform these operations only once per mask order. To enable this, mask salvage processes are essential. Defects are the primary priority and are addressed with cleaning and repair techniques of various types targeted to needs. CD uniformity is addressed with predictive and feedback mapping techniques. CD uniformity is also addressed with post-mask fabrication gray-mask correction and dose correction at the scanner. Mask pattern placement correction by systematic error mapping is done but post-mask-patterning correction represents an opportunity for salvage process development. Until consistently superior mask registration can be achieved during or after patterning, self-aligned wafer processing will continue to be the primary enabling method for optical double-exposure while normal scaling issues will challenge EUV mask development.
It is the ability to perform the high-cost operations only once to create each mask and then recover individual specification parameters with salvage operations which will differentiate mask makers in the future.
Traditionally, definition of mask specifications is done completely by the mask user, while characterization of the mask
relative to the specifications is done completely by the mask maker. As the challenges of low-k1 imaging continue to
grow in scope of designs and in absolute complexity, the inevitable partnership between wafer lithographers and mask
makers has strengthened as well. This is reflected in the jointly owned mask facilities and device manufacturers'
continued maintenance of fully captive mask shops which foster the closer mask-litho relationships. However, while
some device manufacturers have leveraged this to optimize mask specifications before the mask is built and, therefore,
improve mask yield and cost, the opportunity for post-fabrication partnering on mask characterization is more apparent
The Advanced Mask Technology Center (AMTC) has been investigating the concept of assessing how a mask images,
rather than the mask's physical attributes, as a technically superior and lower-cost method to characterize a mask. The
idea of printing a mask under its intended imaging conditions, then characterizing the imaged wafer as a surrogate for
traditional mask inspections and measurements represents the ultimate method to characterize a mask's performance,
which is most meaningful to the user. Surrogate wafer print (SWaP) is already done as part of leading-edge wafer fab
mask qualification to validate defect and dimensional performance.
In the past, the prospect of executing this concept has generally been summarily discarded as technically untenable and
logistically intractable. The AMTC published a paper at BACUS 2007 successfully demonstrating the performance of
SWaP for the characterization of defects as an alternative to traditional mask inspection . It showed that this concept is
not only feasible, but, in some cases, desirable.
This paper expands on last year's work at AMTC to assess the full implementation of SWaP as an enhancement to mask
characterization quality including defectivity, dimensional control, pattern fidelity, and in-plane distortion. We present a
thorough analysis of both the technical and logistical challenges coupled with an objective view of the advantages and
disadvantages from both the technical and financial perspectives. The analysis and model used by the AMTC will serve
to provoke other mask shops to prepare their own analyses then consider this new paradigm for mask characterization
In this paper, we describe the integration of EUV lithography into a standard semiconductor manufacturing flow to
produce demonstration devices. 45 nm logic test chips with functional transistors were fabricated using EUV lithography
to pattern the first interconnect level (metal 1).
This device fabrication exercise required the development of rule-based 'OPC' to correct for flare and mask shadowing
effects. These corrections were applied to the fabrication of a full-field mask. The resulting mask and the 0.25-NA fullfield
EUV scanner were found to provide more than adequate performance for this 45 nm logic node demonstration. The
CD uniformity across the field and through a lot of wafers was 6.6% (3σ) and the measured overlay on the test-chip
(product) wafers was well below 20 nm (mean + 3σ). A resist process was developed and performed well at a sensitivity
of 3.8 mJ/cm2, providing ample process latitude and etch selectivity for pattern transfer. The etch recipes provided good
CD control, profiles and end-point discrimination, allowing for good electrical connection to the underlying levels, as
evidenced by electrical test results.
Many transistors connected with Cu-metal lines defined using EUV lithography were tested electrically and found to
have characteristics very similar to 45 nm node transistors fabricated using more traditional methods.
The International Venture for Nanolithography (INVENT) initiative announced in mid 2005, a unique industry-university
consortium between the College of Nanoscale Science and Engineering at Albany and a group of leading edge
integrated device manufacturers, has launched an extensive R&D program on EUV lithography (EUVL). The overall
scope of the INVENT EUVL program, the status of our efforts to establish a baseline lithography process on a full-field
EUVL scanner, and our progress in evaluating EUV resist materials, in designing a custom reticle for scanner
characterization and in developing an actinic EUV mask imaging microscope, are discussed.
To make immersion lithography a reality in manufacturing, several challenges related to materials and defects must be addressed. Two such challenges include the development of water immersion compatible materials, and the vigorous pursuit of defect reduction with respect to both the films and the processes. Suitable resists and topcoats must be developed to be compatible with the water-soaked environment during exposure. Going beyond the requisite studies of component leaching from films into the water, and absorption of water into the films, application-specific optimization of photoresists and top coats will be required. This would involve an understanding of how a wide array of resist chemistry and formulations behave under immersion conditions. The intent of this paper is to compare lithographic performance under immersion and dry conditions of resists containing different polymer platforms, protecting groups, and formulations. The compatibility of several developer-soluble top-coat materials with a variety of resists is also studied with emphasis on profile control issues. With respect to defects, the sources are numerous. Bubbles and particles created during the imaging process, material remnants from incomplete removal of topcoats, and image collapse as related to resist swelling from water infusion are all sources of yield-limiting defects. Parallel efforts are required in the material development cycle focusing both on meeting the lithographic requirements, and on understanding and eliminating sources of defects. In this paper, efforts in the characterization and reduction of defects as related to materials chemistry and processing effects will be presented.
157 nm has been explored as a lithographic technology for several years on small field imaging tools with encouraging results. Significant progress has occurred in tool platform design, resist performance, and optical material quality. However, a major test of a new lithography comes when full field, scanned images can be produced as this becomes a crucial test of system performance and uniformity. We report on early results from a 22 mm x 26 mm (slot x scan) field Micrascan VII 157 nm lithography scanner obtained using a binary reticle. In addition, a full field alternating phase shift reticle was fabricated on modified fused silica1 and used to extend the imaging capability. Resolution and uniformity data from both reticles will be presented. The lithographic performance will also be compared to simulations using predicted performance from the scanner.
Alternating phase shift reticles are one proposed solution for printing features required at the 90 nm and 65 nm nodes using 193 nm lithography. A key enabler to the adoption of this technology is defect inspection so as to guarantee defect free reticles are delivered to wafer fab production. A test reticle with programmed sub-180 degree phase bump and divot defects has been developed that is representative of the sub-90 nm node. This reticle is characterized by SEM methods. This test reticle in turn is used to determine the defect detection performance of a DUV reticle inspection tool, which uses a phase contrast enhanced optical system to improve the detection of phase defects. This presentation discusses several of the challenges in the design and manufacture of the programmed defect test reticle, the reticle characterization results, and the inspection station results. Defect review methods are described which differentiate between chrome, phase bump, and phase divot defects. Additionally, a best known methodology (BKM) is discussed for the manufacture of alternating phase shift masks based upon detecting killer defects before significant additional value is added.
Microelectronics industry leaders routinely name mask technology and mask supply issues of cost and cycle time as top issues of concern. A survey was initiated in 2002 with support from International SEMATECH (ISMT) and administered by SEMI North America to gather information about the mask industry as an objective assessment of its overall condition.1 This paper presents the results of the second annual survey which is an enhanced version of the inaugural survey building upon its strengths and improving the weak points. The original survey was designed with the input of member company mask technologists, merchant mask suppliers, and industry equipment makers. The assessment is intended to be used as a baseline for the mask industry and the microelectronics industry to gain a perspective on the technical and business status of the critical mask industry. An objective is to create a valuable reference to identify strengths and opportunities and to guide investments on critical-path issues. As subsequent years are added, historical profiles can also be created. This assessment includes inputs from ten major global merchant and captive mask manufacturers representing approximately 80% of the global mask market (using revenue as the measure) and making this the most comprehensive mask industry survey ever. The participating companies are: Compugraphics, Dai Nippon Printing, Dupont Photomask, Hoya, IBM, Infineon, Intel, Taiwan Mask Company, Toppan, and TSMC. Questions are grouped into five categories: General Business Profile Information; Data Processing; Yields and Yield loss Mechanisms; Delivery Time; and Returns and Services. Within each category are a multitude of questions that create a detailed profile of both the business and technical status of the mask industry.
Alternating Phase Shift Masks (altPSM's) are an option for the production of critical layers at the 100 nm technology node and below. Successful implementation of altPSM's into a wafer manufacturing process depends upon the ability to successfully inspect, disposition and repair defects that occur during the mask manufacturing process. One technique previously described to improve phase defect contrast was the use of simultaneous transmitted and reflected light . The previous technique provided for improved phase defect detection in altPSM's produced for the 130 nm node at a 248 nm lithographic wavelength. This work describes the results from a die-to-die inspection method that improves phase defect contrast in transmitted light for altPSM's produced for the 100 nm node at a 193 nm wavelength. The improved phase defect detection technique addresses the challenges of decreasing linewidth/pitch and reduced defect phase resulting from the decrease in lithographic wavelength relative to the inspection wavelength of light. The improved phase defect detection method also provides a method to determine whether a defect is a binary, phase bump or phase divot type of defect. Results are compared against the previous inspection methods. A test vehicle for gathering sensitivity performance data is described along with the results obtained from the inspection system.
Microelectronics industry leaders routinely name mask technology and mask supply issues of cost and cycle time as top issues of concern. A survey was created with support from International SEMATECH (ISMT) and administered by SEMI North America to gather information about the mask industry as an objective assessment of its overall condition. The survey was designed with the input of member company mask technologists, merchant mask suppliers, and industry equipment makers. This assessment can be used as a baseline for the mask industry and the microelectronics industry to gain a perspective on the technical and business status of our critical mask industry. It should serve as a valuable reference to identify strengths and opportunities and to guide investments on critical-path issues.
Questions are grouped into five categories: General Business Profile Information; Data Processing; Yields and Yield loss Mechanisms; Delivery Time; and Returns and Services. Within each category are a multitude of questions that create a detailed profile of both the business and technical status of the critical mask industry.
Alternating Phase Shift Masks (altPSM’s) are an option for the production of critical layers at the 100 nm technology node and below produced at ArF lithographic wavelength. Successful implementation of altPSM’s depends upon the ability to successfully inspect, disposition and repair defects that occur during the manufacturing process.
One technique previously described to improve phase defect contrast was the use of simultaneous transmitted and reflected light. The previously described technique provided for improved phase defect detection in altPSM’s produced for the 130 nm node at a 248 nm lithographic wavelength. This work describes the results from a die-to-die inspection method that improves phase defect contrast in transmitted light for altPSM’s produced for the 100 nm node at a 193 nm wavelength. The improved phase defect detection technique addresses the challenges of decreasing linewidth/pitch and reduced defect phase resulting from the decrease in lithographic wavelength relative to the inspection wavelength of light. The improved phase defect detection method also provides a method to determine whether a defect is a binary, phase bump or phase divot type of defect. Results are compared against the previous inspection methods. A test vehicle for gathering sensitivity performance data is described along with the results obtained from the inspection system.
International SEMATECH (ISMT) is a consortium consisting of 13 leading semiconductor manufacturers from around the globe. Its objective is to develop the infrastructure necessary for its member companies to realize the International Technology Roadmap for Semiconductors (ITRS) through efficiencies of shared development resources and knowledge. The largest area of effort is lithography, recognized as a crucial enabler for microelectronics technology progress. Within the Lithography Division, most of the efforts center on mask-related issues. The development strategy at International SEMATCH will be presented and the interlock of lithography projects clarified. Because of the limited size of the mask production equipment market, the business case is weak for aggressive investment commensurate with the pace of the International Technology Roadmap for Semiconductors. With masks becoming the overwhelming component of lithography cost, new ways of reducing or eliminating mask costs are being explored. Will mask technology survive without a strong business case? Will the mask industry limit the growth of the semiconductor industry? Are advanced masks worth their escalating cost? An analysis of mask cost from the perspective of mask value imparted to the user is presented with examples and generic formulas for the reader to apply independently. A key part to the success for both International SEMATECH and the industry globally will be partnerships on both the local level between mask-maker and mask-user, and the macro level where global collaborations will be necessary to resolve technology development cost challenges.
The Semiconductor Industry has been on a historic productivity growth curve that is due to the feature increase based on size reductions. The pace of technology introduction is accelerating as evidenced by the shortening of time from the introduction of the 180nm node and the introduction of the 130nm node. Historically, the introduction of new nodes had been on a three-year cycle. This raises the question of the impact of this acceleration on the manufacture of masks. This paper examines the impact on semiconductor masks by considering the process steps involved in manufacturing masks and the related cots and cycle time. As technology accelerates, the tools available may not maintain a similar pace of introduction. The consequences of this possible non-compliance with the technology acceleration will have an impact on the cost of masks. An example is employed to demonstrate the financial impact of the technology acceleration. Projections can be made of the continuing impact of technology acceleration on the mask manufacturing process. The conclusions drawn are that several identified, critical processes must be the focus of improvement to allow the industry to continue on the productivity growth curve.
Using alternating phase shifted-mask is an important way to enhance resolution and process window. In this article, the printability of defects of 193 nm alternating phase-shifted mask is reported. We built alternating phase-shifted masks with programmed defects of various types and sizes, and evaluated the impact of each defect on wafer CD. The masks include chrome and phase defects of various phase angles, with defect size down to 10 nm (at 1X size). The Maximum Non-Printable Defect (MNPD) is defined as the maximum defect size that distorts wafer CD less than 10 percent. MNPD of various types of defects were compared on printed wafers for lines and spaces patterns with nominal line width down to 70 nm. A model was created to simulate, further analyze and correlate the experimental results. The simulation also allows for extension beyond the experiment parameter space.
We have developed a novel Si-based composite thin film for attenuated phase shift mask(APSM) applications at 193/157 nm wavelength. The fabrication involved sputtering deposition, either with dual target or a single composite target. At 193 nm, these thin films show tunable optical transmission and good stability against long term radiation, common chemicals used to strip photoresist, and exhibit good dry etch selectivity to quartz. Specifically, a film with initial transmission of 5.72%,the total increase oftransmission was 0.27% for doses up to 5.4 kJ/cm2. Also, the increase of transmission was 0.19% after 60 mm of cleaning treatment in acid based solution (H2S04H20210:1 at 95°C). The dry etch selectivity over fused quartz was greater than 5:1. The transmission of the films at 193 nm can be tuned from 0 % to 20 % by varying the thin film composition, process gas flow and composition, and deposition pressure. This wide transmission window provides the possible extension down to 157 nm wavelength.
Mask technology development has accelerated dramatically in recent years from the glacial pace of the last three decades to the rapid and sometimes simultaneous introductions of new wavelengths and mask-based resolution enhancement techniques. The nature of the semiconductor business has also become one driven by time-to-market as an overwhelming factor in capturing market share and profit. These are among the factors that have created enormous stress on the mask industry to produce masks with enhanced capabilities, such as phase-shifting attenuators, sub-resolution assist bars, and optical proximity correction (OPC) features, while maintaining or reducing cost and cycle time. The mask can no longer be considered a commodity item that is purchased form the lowest-cost supplier. Instead, it must now be promoted as an integral part of the technical and business case for a total lithographic solution. Improving partnership between designer, mask-maker, and wafer lithographer will be the harbinger of success in finding a profitable balance of capability, cost, and cycle time. Likewise for equipment infrastructure development, stronger partnership on the international level is necessary to control development cost and mitigate schedule and technical risks.
The manufacturing implementation of alternating aperture PSM's (AltPSM) has been gated by the impacts these techniques have on reticle manufacturing, specifically reticle defect inspection and repair. Die-to-die inspection techniques have been achieved for some clearfield multiphase alternate phase reticles, but the required die-to-database solutions are not currently available with defect inspection systems. In response to these mask manufacturing issues and IC design layout issues, resolution enhancing techniques based on Darkfield Alternate Phase (DAP) reticle designs are now of growing importance. A DAP Programmed Evaluation Reticle, DAPPER, was fabricated and inspected on a new high numerical aperture ultraviolet reticle inspection system. The results show reasonable defect sensitivity performance in the presence of both reticle geometry and quartz etch topography characteristic of 130-nm node advanced logic circuit DAP reticles.
The Microlithographic Mask Development Center (MMD) has been the focal point of X-ray mask development efforts in the United States since its inception in 1993. Funded by the Advanced Research Projects Agency (ARPA), and with technical support from the Proximity X-ray Lithography Association (AT&T, IBM, Loral Federal Systems, and Motorola) the MMD has recently made dramatic advances in mask fabrication. Numerous defect-free 64Mb and 256Mb DRAM masks have been made on both boron-doped silicon and silicon carbide substrates. Image-placement error of less than 35nm 3 sigma is achieved with high yield. Image-size (critical dimension) control of 25nm 3 sigma on 250nm nominal images is representative performance. This progress is being made in a manufacturing environment with significant volumes, multiple customers, multiple substrate configurations, and fast turnaround-time (TAT) requirements. The MMD state-of-the-art equipment infrastructure has made much of this progress possible. This year the MMD qualified the EL-4, an IBM-designed-and-built variable-shaped-spot e-beam system. The fundamental performance parameters of this system will be described. Operational techniques of multiple partial exposure writing and product specific emulation (PSE) have been implemented to improve image-placement accuracy with remarkable success. Image-size control was studied in detail with contributory components separated. Defect density was systematically reduced to yield defect-free masks while simultaneously tightening inspection criteria. Information about these and other recent engineering highlights will be reported. An outline of the primary engineering challenges and goals for 1996 and status of progress toward 100 nm design rule capability will also be given.
The Microlithographic Mask Development Center (MMD) was established as the X-ray mask manufacturing facility at the IBM Microelectronics Division semiconductor fabricator in Essex Junction, Vermont. This center, in operation for over two years, produces high yielding, defect-free X-ray masks for competitive logic and memory products at 250nm groundrules and below. The MMD is a complete mask facility that manufactures silicon membrane mask blanks in the NIST format and finished masks with electroplated gold X-ray absorber. Mask patterning, with dimensions as small as 180 nm, is accomplished using IBM-built variable shaped spot e-beam systems. Masks are routinely inspected and repaired using state-of-the-art equipment: two KLA SEM Specs for defect inspection, a Leica LMS 2000 for image placement characterization, an Amray 2040c for image dimension characterization and a Micrion 8000 XMR for defect repair. This facility maintains a baseline mask process with daily production of 250nm, 32Mb SRAM line monitor masks for the continuous improvement of mask quality and processes. Development masks are produced for several semiconductor manufacturers including IBM, Motorola, Loral, and Sanders. Masks for 64Mb and 256Mb DRAM (IBM) and advanced logic/SRAM (IBM and Motorola) designs have also been delivered. This paper describes the MMD facility and its technical capabilities. Key manufacturing metrics such as mask turnaround time, parametric yield learning and defect reduction activities are highlighted. The challenges associated with improved mask quality, sub-180nm mask fabrication, and the transition to refractory metal absorber are discussed.
A continuing trend in X-ray lithography is the requirement for high accuracy masks. Image placement, or the ability to pattern images in the correct locations, is one of the most critical requirements. It is driven by a number of parameters, including the electron-beam lithography system and precision of the metrology system. Also, because the X-ray mask substrate consists of a thin membrane, it is very susceptible to the stresses of the resist film, absorber material, and plating base. An extensive analysis of the contributors to image placement was performed to determine the relative contribution of each. This analysis highlighted those contributors which caused the largest distortions and which, therefore, presented the most opportunities for improvement. Several changes were then implemented which resulted in a 50 percent overall improvement to placement of the X-ray mask images. The experimental design and detailed results are discussed.
This paper presents the results of a study to explicitly assess the performance of silicon carbide masks by directly measuring overlay accuracy and precision of exposures made on a state-of-the-art commercially available x-ray stepper, the Suss XRS200/3. The work was done using a mask fabricated at IBM from silicon carbide coated wafers obtained from HOYA Electronics Corp. with exposures completed at IBM's Advanced Lithography Facility (ALF) using synchrotron-generated radiation. The mask pattern design contains many overlay measurement fiducials, resolution patterns, and alignment verniers, and two sets of three alignment marks: one set inboard (kerf) and one set outboard. The performance of an imaging-based alignment system, such as the ALX system on the Suss XRS200/3 steppers, varies depending upon the optical characteristics of the alignment marks on the mask and wafer.
This paper describes the evolution of a simple recirculating etch station into a successful x-ray mask membrane-etch station. The manufacturing etch station consists of a large, heated mix tank in which she ethanolamine solution is brought to reaction temperature. The etchant is then pumped into a smaller heated process tank and is continuously recirculated through a filter between the two tanks. Up to 50 substrates can be processed during one product run. Both tanks and wetted parts are made of Teflon. Salient features of the membrane-etch station include dual Pyrex reflux columns, a nitrogen blanket throughout the systems to prevent oxygen infiltration, special high-temperature Teflon and Gore-tex seals for the mix and process tank lids, and a Teflon filter in the recirculating line between the mix and process tanks. Subsequent tooling improvements included improving the thermal sensors and installing more powerful heaters. Tool qualification tests have demonstrated the membrane-etch station ready for manufacturing use. The manufacturing etch station has increased our etch capacity by almost an order of magnitude and is currently being used to produce silicon membranes for x-ray mask substrates.