An accurate model for the self-stop copper chemical mechanical polishing (Cu-CMP) process has been developed using
CMP modeling technology from Mentor Graphics. This technology was applied on data from Sony to create and optimize
copper electroplating (ECD), Cu-CMP, and barrier metal polishing (BM-CMP) process models. These models take into
account layout pattern dependency, long range diffusion and planarization effects, as well as microloading from local
pattern density. The developed ECD model accurately predicted erosion and dishing over the entire range of width and
space combinations present on the test chip. Then, the results of the ECD model were used as an initial structure to model
the Cu-CMP step. Subsequently, the result of Cu-CMP was used for the BM-CMP model creation. The created model
was successful in reproducing the measured data, including trends for a broad range of metal width and densities. Its
robustness is demonstrated by the fact that it gives acceptable prediction of final copper thickness data although the
calibration data included noise from line scan measurements. Accuracy of the Cu-CMP model has a great impact on the
prediction results for BM-CMP. This is a critical feature for the modeling of high precision CMP such as self-stop Cu-CMP. Finally, the developed model could successfully extract planarity hotspots that helped identify potential problems
in production chips before they were manufactured. The output thickness values of metal and dielectric can be used to drive layout enhancement tools and improve the accuracy of timing analysis.
As the technology node shrinks, printed-wafer shapes show progressively less similarity to the design-layout shapes, even with optical proximity correction (OPC). Design tools have a restricted ability to address this shape infidelity. Their understanding of lithography effects is limited, taking the form of design rules that try to prevent "Hot Spots" - locations that demonstrate wafer-printing problems. These design rules are becoming increasingly complex and therefore less useful in addressing the lithography challenges. Therefore, design tools that have a better understanding of lithography are becoming a necessity for technology nodes of 65 nm and below. The general goal of this work is to correct lithography Hot Spots during physical-design implementation. The specific goal is to automatically fix a majority of the Hot Spots in the Metal 2 layers and above, with a run time on the order of a few hours per layer. Three steps were taken to achieve this goal. First, Hot Spot detection was made faster by using rule-based detection. Second, Hot Spot correction was automated by using rule-based correction. Third, convergence of corrections was avoided by performing correction locally, which means that correcting one Hot Spot was very unlikely to create new Hot Spots.
KEYWORDS: Data modeling, Lithography, Optical proximity correction, Resolution enhancement technologies, Photomasks, Design for manufacturing, Design for manufacturability, Manufacturing, Control systems, System integration
Systematic design for manufacturability ( DfM ) scheme including triple gates for hot spot elimination under the low-k1 lithography condition is proposed and efficient approaches to the hot spot elimination at each development stage in the DfM scheme are discussed in view of the actual situation under the concurrent development of design rule ( DR ), layout, process, optical proximity correction ( OPC ) and resolution enhancement technique ( RET ) technologies. Integrated-type lithography simulation system with OPC tool is much available for the fast processing at the initial stage and promising to be complementarily used for the verification of chip-level layout with conventional-type one at the final development stage. Low order of the lithography empirical model originating moderate prediction accuracy for all kinds of patterns is hopeful to be used at the initial development stage because it is difficult to obtain a lot of reliable experimental data for making the accurate empirical lithography model due to frequent improvement of the process, OPC and RET technologies. At the final development stage, sufficient and reliable experimental data for device pattern variations allow us to implement the higher order of the empirical model. The DfM scheme with efficient approaches in view of the actual situation under the concurrent development is found to be promising for the robust pattern formation under the low-k1 lithography condition.
Focus monitor technology for attenuated phase shift masks under annular illumination has been developed for a in-line quality control. The focus monitor pattern on a reticle employs a pair of grouped lozenge-shaped opening patterns in the attenuated phase shifting region. Since the phase shifting angles of light passing through the first and second opening patterns are 90° and 0°, respectively, the best focus position for the first pattern shifts to that of the second pattern. Subtraction of the length of the patterns is a linear function of the actual focal position printed on the wafer. The linear function is insensitive to further mask phase error. Therefore, the effective focal position can be extracted by measuring that subtracted from the measured length. High resolution of 10 nm defocus was achieved using this technique.
In recent low-k1 lithography, OPC is required to generate more aggressively fragmented patterns to keep its pattern fidelity on the LSI devices. But over-aggressive OPC might induce a crisis of mask manufacturability. In this paper, using newly defined parameter, DPF (Degree of Pattern Fidelity), quantitative relations between OPC aggressiveness and pattern fidelity are evaluated under several conditions. Next, the concept of MEF is extended for 2D complex patterns using DPF, and is evaluated as a function of OPC aggressiveness. Other mask manufacturability, such as writing time, data volume, and inspection availability would be evaluated as a function of OPC aggressiveness.
A focus monitor technology for attenuated PSM under annular illumination has been developed as an in-line quality control. The focus monitor pattern on a reticle employs a pair of grouped lozenge-shaped opening patterns in attenuated phase shifting region. Since the phase shifting angles of the light passing through the first and second opening patterns are 90 degrees and 180 degrees, respectively, the best focus position for the first pattern shifts to that for the second pattern. The subtraction of the length of the patterns is a linear function of the actual focal position printed on the wafer. Therefore, the effective focal position can be extracted by measuring the subtraction of the measured length. A high resolution of 10-nm defocus could be achieved by this technique.
We have developed in-line dose and focus monitoring techniques for the detailed analysis of critical dimension error and accurate process control. From exposed wafers, effective does and focus are measured with specificed monitor marks built on a reticle. The contributions of effective dose and focus to critical dimension error on device chips were clarified in a fabrication proces of 110 nm isolated pattern with a KrF scanner. The critical dimensions error was described as a function of effective dose and focus, which include various process fluctuations. We could determine whether current exposure settings such as dose input and focus input were adequate or not. Based on the experimental data, we estimated the benefit of simultaneous Run-to-Run control of dose and focus. The estimation clarifies that it realizes total critical dimension control including Run-to-Run and intra-Run.
We have established effective dose metrology using a dose monitor mark named the effective dose meter, which has no focus response. By placing the effective dose meter onto the scribe line in a device reticle, in-line monitoring of the effective dose on a product has been realized. The effective dose meter is designed to monitor the effective dose as a resist line length whose dimension is detectable with an optical measurement tool. The design is considered to have no impact on both reticle fabrication and wafer processing. By monitoring with the effective dose meter, the contribution of effective dose error to critical dimension variation is obtained independently of focus error. Dose budget analysis from the in-line effective-dose monitor clarifies the current process ability on reticle linewidth variation and resist processing uniformity. This paper describes the mark design and the analysis result of the in-line effective dose monitor in device fabrication with KrF lithography.
We have established the effective dose metrology using a dose monitor mark named the effective dose-meter that has no focus response. By arranging the effective dose-meter onto scribe line in a device reticle, the in-line monitor of effective dose on product has been realized. The effective dose-meter was designed to monitor effective dose as a resist line length whose dimension is detectable with an optical measurement tool. The design is considered not to impact on both reticle fabrication and wafer processing. By monitoring the effective dose-meter, the contribution of effective dose error to critical dimension variation could be obtained independently with focus error. Dose budget analysis from in-line effective dose monitor made clear the current process ability with respect to reticle linewidth variation and resist processing uniformity. This paper describes the mark design, and the analysis result of in- line effective dose monitor in device fabrication with KrF lithography.
An accurate measurement technique for effective exposure dose in optical microlithography has been developed. The effective exposure dose can be obtained by a dose monitor mark in a photomask named effective dose-meter, consisting of plural segments including grating patterns with a pitch below the resolution limit and different duty ratios gradually. Since the effective dose-meter does not resolve on a wafer but it makes flood exposure with the dose as a function of the duty ratio, residual thickness of the photoresist after development changes according to the duty ratio. Therefore, the effective exposure dose can be obtained by grasping the duty ratio of the grating patterns in the effective dose-meter corresponding to the position that the photoresist had cleared completely. A calibration technique utilizing an aerial image measurement system also has been proposed to avoid the influence of intra- wafer process variation. The advantages of this method are (1) completely focus-free, (2) the effective dose-meter is small enough to ignore the influence of the intra-wafer process variation on the accuracy, and (3) highly dose resolution of less than 0.5%. It was found that this technique function effectively. The variation of the effective exposure dose in a wafer in the current krypton-fluoride-excimer-laser lithography process was measured as a demonstration of this technology.
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