Over the past few years, patterning edge placement error (EPE) has been established as the key metric for patterning budget generation. In previous work  it has been shown that local variability of contact within 28nm node SRAM regular array accounts for more than 90% of total variability. Among the most obvious source of local variability, we can think of optical proximity correction (OPC), mask process, wafer process (litho and etch). If one would like to make breakdown between these sources, process related sources will be very measurement consuming to characterize, and even more complex to correct. On the opposite, OPC can be characterized computationally as well as corrected. Therefore, this paper proposes a computational method to evaluate and correct pattern variability induced by OPC within regular array layout. In a different field of application, array of pixels in imager SoC is very sensitive to pattern variability, especially when it is periodic. This is known as MURA effect, and many works have shown this effect in the field of flat panel display . The challenge is similar in the field of image SoC. Once again, OPC variability is also a contributor to this effect. Therefore, array of pixels is also benefitting from the method proposed in this paper.
At 28nm technology node and below, hot spot prediction and process window control across production wafers have become increasingly critical to prevent hotspots from becoming yield-limiting defects. We previously established proof of concept for a systematic approach to identify the most critical pattern locations, i.e. hotspots, in a reticle layout by computational lithography and combining process window characteristics of these patterns with across-wafer process variation data to predict where hotspots may become yield impacting defects [1,2]. The current paper establishes the impact of micro-topography on a 28nm metal layer, and its correlation with hotspot best focus variations across a production chip layout. Detailed topography measurements are obtained from an offline tool, and pattern-dependent best focus (BF) shifts are determined from litho simulations that include mask-3D effects. We also establish hotspot metrology and defect verification by SEM image contour extraction and contour analysis. This enables detection of catastrophic defects as well as quantitative characterization of pattern variability, i.e. local and global CD uniformity, across a wafer to establish hotspot defect and variability maps. Finally, we combine defect prediction and verification capabilities for process monitoring by on-product, guided hotspot metrology, i.e. with sampling locations being determined from the defect prediction model and achieved prediction accuracy (capture rate) around 75%
28nm metal 90nm pitch is one of the most challenging processes for computational lithography due to the resolution limit of DUV scanners and the variety of designs allowed by design rules. Classical two dimensional hotspot simulations and OPC correction isn’t sufficient to obtain required process windows for mass production. This paper shows how three dimensional resist effects like top loss and line end shortening have been calibrated and used during the OPC process in order to achieve larger process window. Yield results on 28FDSOI product have been used to benchmark and validate gain between classical OPC and R3D OPC.
At the 28nm technology node and below, hot spot prediction and process window control across production wafers have become increasingly critical. We establish proof off concept for ASML’s holistic lithography hot spot detection and defect monitoring flow, process window optimizer (PPWO), for a 228nm metal layer process. We demonstrate prediction and verification of defect occurrence on wafer that arise from focus variations exceeding process window margins of device hotspots. We also estimate the improvement potential if design aware scanner control was applied.
The NXE:3300B is ASML’s third generation EUV system and has an NA of 0.33 and is positioned at a resolution of 22nm, which can be extended down to 18nm and below with off-axis illumination at full transmission. Multiple systems have been qualified and installed at customers. The NXE:3300B succeeds the NXE:3100 system (NA of 0.25), which has allowed customers to gain valuable EUV experience. It is expected that EUV will be adopted first for critical Logic layers at 10nm and 7nm nodes, such as Metal-1, to avoid the complexity of triple patterning schemes using ArF immersion. In this paper we will evaluate the imaging performance of (sub-)10nm node Logic M1 on the NXE:3300B EUV scanner. We will show the line-end performance of tip-to-tip and tip-to-space test features for various pitches and illumination settings and the performance enhancement obtained by means of a 1st round of OPC. We will also show the magnitude of local variations. The Logic M1 cell is evaluated at various critical features to identify hot spots. A 2nd round OPC model was calibrated of which we will show the model accuracy and ability to predict hot spots in the Logic M1 cell. The calibrated OPC model is used to predict the expected performance at 7nm node Logic using off-axis illumination at 16nm minimum half pitch. Initial results of L/S exposed on the NXE:3300B at 7nm node resolutions will be shown. An outlook is given to future 0.33 NA systems on the ASML roadmap with enhanced illuminator capabilities to further improve performance and process window.
From 28 nm technology node and below optical proximity correction (OPC) needs to
take into account light scattering effects from prior layers when bottom anti-reflective coating
(BARC) is not used, which is typical for ionic implantation layers. These effects are complex,
especially when multiple sub layers have to be considered: for instance active and poly structures
need to be accounted for.
A new model form has been developed to address this wafer topography during model
calibration called the wafer 3D+ or W3D+ model. This model can then be used in verification
(using Tachyon LMC) and during model based OPC to increase the accuracy of mask correction
and verification. This paper discusses an exploration of this new model results using extended
wafer measurements (including SEM). Current results show good accuracy on various
The objective of this paper is to extend the ability of a more stable overall process control for the 28 nm Metal layer. A method to better control complex 2D-layout structures for this node is described. Challenges are coming from the fact that the structures, which limit the process window are mainly of 2D routing nature and are difficult to monitor. Within the framework of this study the emphasis is on how to predict these process-window-limiting structures upfront, to identify root causes and to assist in easier monitoring solutions enhancing the process control. To address those challenges, the first step is the construction of a reliable Mask-3D and Resist-3D model. Advanced 3Dmodeling allows better prediction of process variation upfront. Furthermore it allows highlighting critical structures impacted by either best-focus shifts or by low-contrast resist-imaging effects, which then will be transferred non-linearly after etch. This paper has a tight attention on measuring the 3D nature of the resist profiles by multiple experimental techniques such as Cross-section scanning electron microscopy methods (X-SEM) and atomic force microscopy (AFM). Based on these measurements the most reliable data are selected to calibrate full-chip Resist-3D model with. Current results show efficient profile matching among the calibrated R3D model, wafer AFM and X-SEM measurements. In parallel this study enables the application of a new metric as result of the resist profiles behavior in function of exposure dose. In addition it renders the importance on the resist shape. Together these items are reflected to be efficient support on process optimization and improvement on the process control.
The low-k1 domain of immersion lithography tends to result in much smaller depths of focus (DoF) compared to prior technology nodes. For 28 nm technology and beyond it is a challenge since (metal) layers have to deal with a wide range of structures. Beside the high variety of features, the reticle induced (mask 3D) effects became non-negligible. These mask 3D effects lead to best focus shift. In order to enhance the overlapping DoF, so called usable DoF (uDoF), alignment of each individual features best focus is required. So means the mitigation of the best focus shift. This study investigates the impact of mask 3D effects and the ability to correct the wavefront in order to extend the uDoF. The generation of the wavefront correction map is possible by using computational lithographic such Tachyon simulations software (from Brion). And inside the scanner the wavefront optimization is feasible by applying a projection lens modulator, FlexWaveTM (by ASML). This study explores both the computational lithography and scanner wavefront correction capabilities. In the first part of this work, simulations are conducted based on the determination and mitigation of best focus shift (coming from mask 3D effects) so as to improve the uDoF. In order to validate the feasibility of best focus shift decrease by wavefront tuning and mitigation results, the wavefront optimization provided correction maps are introduced into a rigorous simulator. Finally these results on best focus shift and uDoF are compared to wafers exposed using FlexWave then measured by scanning electron microscopy (SEM).
KEYWORDS: Lithography, Electron beam lithography, Data modeling, Calibration, 3D modeling, Atomic force microscopy, Scanning electron microscopy, Double patterning technology, Data centers, Photoresist processing
The pursuit of ever smaller transistors has pushed technological innovations in the field of lithography. In order
to continue following the path of Moore’s law, several solutions have been proposed: EUV, e-beam and double
patterning lithography. As EUV and e-beam lithography are still not ready for mass production for 20 nm and 14 nm
nodes, double patterning lithography play an important role for these nodes. In this work, we focus on a Self-Aligned
Double-Patterning process (SADP) which consists of depositing a spacer material on each side of a mandrel exposed
during a first lithography step, dividing the pitch into two, after being transferred into the substrate, and then cutting the
unwanted patterns through a second lithography exposure.
In the specific case where spacers are deposited directly on the flanks of the resist, it is crucial to control its
profile as it could induce final CD errors or even spacer collapse. One possibility to prevent these defects from occurring
is to predict the profile of the resist at the OPc verification stage. For that, we need an empirical resist model that is able
to predict such behaviour.
This work is a study of a profile-aware resist model that is calibrated using both atomic force microscopy
(AFM) and scanning electron microscopy (SEM) data, both taken using a focus and exposure matrix (FEM).
Full chip verification has become a key component of the optical proximity correction (OPC) methodology over the last
decade. Full field verification to catch cross-field effects based on scanner information is becoming increasingly
important in lithography verification. Lithographic Manufacturing Check (LMC) performed with the Brion Tachyon
engine, which is the industry reference tool, now provides the capability to predict wafer CD variations across the entire
field through process windows. LMC is catching and reporting weak lithographic points having small process windows
or excessive sensitivities to mask errors based on the simulation from models with ASML scanner specific parameters.
ASML scanner intra-field information such as dose, focus, flare, illuminator map, aberration data or mask bias map can
be integrated into the LMC run to create an across-field verification and can improve the accuracy of the prediction at
different field locations. In this study we compare such across-field LMC verification with a reference LMC without any
scanner specific data.
Scanner information was loaded into the LMC model by using the Scanner Fingerprint File (SFF) functionality. Various
across field LMC runs using scanner information have been performed and analysed to identify critical design hotspots
or scanner drifts and compared with wafer measurement.
Full field Tachyon LMC results on 40nm Poly and 28nm Metal1 layer are presented. The goal is to investigate the
impact of mask, lens aberrations, illuminator, dose and focus map. This investigation includes wafer validation of the
methodology on identified critical hot spots.
The 22-nm technology node presents a real breakthrough compared to previous nodes in the way that state of the
art scanner will be limited to a numerical aperture of 1.35. Thus we cannot "simply" apply a shrink factor from
the previous node, and tradeoffs have to be found between Design Rules, Process integration and RET solutions
in order to maintain the 50% density gain imposed by the Moore's law. One of the most challenging parts to
enable the node is the ability to pattern Back-End Holes and Metal layers with sufficient process window. It is
clearly established that early process for these layers will be performed by double patterning technique coupled
with advanced OPC solutions.
In this paper we propose a cross comparison between possible double patterning solutions: Pitch Splitting (PS)
and Sidewall Image Transfer (SIT) and their implication on design rules and CD Uniformity. Advanced OPC
solutions such as Model Based SRAF and Source Mask Optimization will also be investigated in order to ensure
good process control.
This work is a part of the Solid's JDP between ST, ASML and Brion in the framework of Nano2012 sponsored
by the French government.
Source Mask Optimization (SMO) technique is an advanced RET with the goal of extending optical lithography lifetime by enabling low k1 imaging [1,2]. Most of the literature concerning SMO has so far focused on PV (process variation) band, MEEF and PW (process window) aspects to judge the performance of the optimization as in traditional OPC . In analogy to MEEF impact for low k1 imaging we investigate the source error impact as SMO sources can have rather complicated forms depending on the degree of freedom allowed during optimization.
For this study we use Tachyon SMO tool on a 22nm metal design test case. A free form and parametric source solutions are obtained using MEEF and PW requirements as main criteria. For each type of source, a source perturbation is introduced to study the impact on lithography performance. Based on the findings we conclude on the choice of freeform or parametric as a source and the importance of source error in the optimization process.
In the continuous battle to improve critical dimension (CD) uniformity, especially for 45-nanometer (nm) logic
advanced products, one important recent advance is the ability to accurately predict the mask CD uniformity
contribution to the overall global wafer CD error budget. In most wafer process simulation models, mask error
contribution is embedded in the optical and/or resist models. We have separated the mask effects, however, by
creating a short-range mask process model (MPM) for each unique mask process and a long-range CD
uniformity mask bias map (MBM) for each individual mask. By establishing a mask bias map, we are able to
incorporate the mask CD uniformity signature into our modelling simulations and measure the effects on global
wafer CD uniformity and hotspots. We also have examined several ways of proving the efficiency of this
approach, including the analysis of OPC hot spot signatures with and without the mask bias map (see Figure 1)
and by comparing the precision of the model contour prediction to wafer SEM images. In this paper we will
show the different steps of mask bias map generation and use for advanced 45nm logic node layers, along with
the current results of this new dynamic application to improve hot spot verification through Brion Technologies'
model-based mask verification loop.
As scanner projection lens captures only a finite number of IC pattern diffraction orders. This low
pass filtering leads to a range of optical proximity effects such as pitch-dependent CD variations,
corner rounding and line-end pullback, resulting in imaged IC pattern excursions from the
intended designs. These predictable OPEs are driven by the imaging conditions, such as
wavelength, illuminator layout, reticle technology, and lens numerical aperture. To mitigate the
pattern excursion due to OPEs, the photolithography community developed optical proximity
correction methodologies, adopted and refined by the EDA industry. In the current
implementations, OPC applied to IC designs can correct layouts to compensate for OPEs and to
provide imaged patterns meeting the design requirements.
Whenever an OPC calibration wafer is exposed, there will be an unavoidable and perhaps non-representative level of
aberration at that part of the exposure field corresponding to where the calibration pattern is written on the mask. In
practice these aberrations values will vary across both the field and from exposure tool to exposure tool. The OPC
engineer is therefore faced with the question of whether the aberrations specific to this part of the reticle field and hence
lens should be taken into account during model fitting. Methodologies have been developed to allow OPC model
calibration when the aerial image is asymmetric either due to the test pattern or the aberrations in the lens that lead to
this. This will be referred to as asymmetry aware model calibration. These methodologies allow asymmetric test
structures to be added to the calibration set to allow greater pattern coverage and therefore allow for a better overall
model fit. Asymmetric calibration structures tend also to be particularly sensitive to asymmetric lens aberrations such as
Coma. The question becomes whether the calibration fit should include asymmetric structures and hence account for
coma, or consider only symmetrical, coma-insensitive structures when doing a model fit.
The paper will investigate, using actual model calibration measurement data the suitability of accounting for model
coma in an actual OPC model calibration.
Good OPC model calibration structures should be representative of and span the dimensions and layout forms that will be found in the product on which the model will be applied. If model fitting is done using edge placement (EPE) methods, only symmetric structures can be used and this constrains the model fitter to a classic but limited set of calibration structures. The most critical features, such as those from a bit cell tend to be asymmetric. While asymmetric structures have typically been used for model verification, using them in model calibration structures provides more degrees of freedom for the calibration test structures to capture two dimensional behavior. This produces more robust, accurate models which yield better quality corrections on wafer. During process development models are re-calibrated as the process is adjusted and optimized. In some cases particularly important critical configurations can be added to the calibration set to insure maximum accuracy on those features. As these configurations are extracted from real designs, they are rarely symmetric. This paper describes how by using a CD-based rather than an edge-placement based modeling approach, OPC models can be created from asymmetric, more product-like type structures, and demonstrates how this can allow better predictability on other verification structures. The paper will also review the two types of model forms commonly used (Constant and Variable Threshold models) and compare their performance while using asymmetric calibration structures.
Flare is known to be responsible for a contrast lost and a process latitude reduction. Another undesirable effect is the flare variation, which induces linewidth variation. For a stepper, this is mainly an intrafield effect. In the same way, the main contribution of flare variation comes also from the across field flare variation (AFFV). In comparison the contribution to across wafer flare variation is weak. Using a scanner, AFFV and flare mean for an isolated field has been reduced by a factor of two. Unfortunately, stray light variation across the wafer has increased, but AWFV and flare mean with adjacent field has not dropped significantly. In this paper, the averaged flare, AFFV and AWFV will be compared on a 248 nm stepper ASM/300, a scanner ASM/500 and 193 nm scanner ASM/900. Different parameters such as field size, bottom anti reflective coating, adjacent field and exposure at the edge of the wafer will be analyzed on mean flare value, AFFV and AWFV. An averaged flare for isolate field and AFFV improvement has been observed for the scanner. However, flare impact needs to be carefully considered because AWFV and flare mean with adjacent field is still not negligible. Flare value seems also to drop significantly with the wavelength change, but more experiments need to be done on this non mature technology.